HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 104

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority.
When the RES pin goes Low, all current processing is halted and the H8/532 chip enters the reset
state.
A reset initializes the internal status of the CPU and the registers of the on-chip supporting
modules and I/O ports. It does not initialize the on-chip RAM.
When the RES pin returns from Low to High, the H8/532 chip comes out of the reset state and
begins executing the hardware reset sequence.
4.2.2 Reset Sequence
The Reset signal is detected when the RES pin goes Low.
To ensure that the H8/532 is reset, the RES pin should be held Low for at least 20ms at power-up.
To reset the H8/532 during operation, the RES pin should be held Low for at least 6 ø clock
cycles. See table D-1, “Status of Ports” in Appendix D for the status of other pins in the reset
state.
When the RES pin returns to the High state after being held Low for the necessary time, the
hardware reset exception-handling sequence begins, during which:
1. The value at the mode pins (MD
2. In the status register (SR), the T bit is cleared to disable the trace mode, and the interrupt mask
3. The CPU loads the reset start address from the vector table into the program counter and begins
The contents of the vector table differs between minimum mode and maximum mode as indicated
in figure 4-2. This affects step 3 as follows:
Minimum mode: One word is copied from addresses H'0000 and H'0001 in the vector table to
the program counter. Program execution then begins from the address in the program counter
(PC).
control register (MDCR).
level (bits I2 to I0) is set to 7. A reset disables all interrupts, including NMI.
executing the program at that address.
2
to MD
0
) is latched in bits MDS2 to MDS0 of the mode
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