HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 111

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

4.6 Invalid Instruction
An invalid instruction exception occurs if an attempt is made to execute an instruction with an
undefined operation code or illegal addressing mode specification. The program counter value
pushed on the stack is the value of the program counter when the invalid instruction code was
detected.
In the invalid instruction exception-handling sequence the T bit of the status register is cleared to
“0,” but the interrupt mask level (I2 to I0) is not affected.
4.7 Trap Instructions and Zero Divide
A trap exception occurs when the TRAPA or TRAP/VS instruction is executed. A zero divide
exception occurs if an attempt is made to execute a DIVXU instruction with a zero divisor.
In the exception-handling sequences for these exceptions the T bit of the status register is cleared
to “0,” but the interrupt mask level (I2 to I0) is not affected. If a normal interrupt is requested
while a trap or zero-divide instruction is being executed, after the trap or zero-divide exception-
handling sequence, the normal interrupt exception-handling sequence is carried out.
4.8 Cases in Which Exception Handling is Deferred
In the cases described next, the address error exception, trace exception, external interrupt (NMI,
IRQ
but are deferred until after the next instruction has been executed.
4.8.1 Instructions that Disable Interrupts
Interrupts are disabled immediately after the execution of five instructions: XORC, ORC, ANDC,
LDC, and RTE.
Suppose that an internal interrupt is requested and the interrupt controller, after checking the
interrupt priority and interrupt mask level, notifies the CPU of the interrupt, but the CPU is
TRAPA Instruction: The TRAPA instruction always causes a trap exception. The TRAPA
instruction includes a vector number from 0 to 15, allowing the user to provide up to sixteen
different trap-handling routines.
TRAP/VS Instruction: When the TRAP/VS instruction is executed, a trap exception occurs if
the overflow (V) bit in the condition code register is set to “1.” If the V bit is cleared to “0,” no
exception occurs and the next instruction is executed.
DIVXU Instruction with Zero Divisor: An exception occurs if an attempt is made to divide
by zero in a DIVXU instruction.
0
, and IRQ
1
) requests, and internal interrupt requests (19 types) are not accepted immediately
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