HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 113

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
(Example)
ADD.W R2,R0
MOV.W R0,@H'FF00
MOV.W #H'FF02,R0
Exception Factor
Trace
Interrupt
Trap
Zero divide
(DIVXU)
4.9 Stack Status after Completion of Exception Handling
The status of the stack after an exception-handling sequence is described below.
Table 4-3 shows the stack after completion of the exception-handling sequence for various types
of exceptions in the minimum and maximum modes.
Table 4-3 Stack after Exception Handling Sequence
Note: The RTE instruction returns to the next instruction after the instruction being executed when
.
.
.
.
.
.
.
.
the exception occurred.
SP
Next instruction address (upper byte)
Next instruction address (lower byte)
Minimum Mode
SR (upper byte)
SR (lower byte)
Program flow
DTC interrupt request
After data transfer cycle, CPU
executes next instruction before
branching to exception handling
94
Data transfer cycle
TP:SP
To NMI exception-handling sequence
Next instruction address (upper byte)
Next instruction address (lower byte)
Next instruction page (8 bits)
Maximum Mode
SR (upper byte)
SR (lower byte)
NMI interrupt request
Don’t-care

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