HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 119

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

Coding Examples:
To select the rising edge of the NMI input:
To select the falling edge of the NMI input:
IRQ
and/or a watchdog timer overflow. A Low IRQ
request enable 0 bit (IRQ
accepts the interrupt. Otherwise the request will be ignored. A watchdog timer overflow requests
an IRQ
timer's control/status register. See section 13, “Watchdog Timer” for details of the watchdog
timer.
The IRQ
value in the upper four bits of IPRA. If bit 4 of data transfer enable register A (DTEA) is set to
“1,” an IRQ
CPU.
In the CPU interrupt-handling sequence for IRQ
and the interrupt mask level is set to the value in the upper four bits of IPRA.
Coding Examples:
To enable IRQ
To assign priority level 7 to IRQ
To have IRQ
IRQ
IRQ
the P1CR is set to “1.”
The IRQ
corresponding value in the lower four bits of IPRA. If bit 0 of data transfer enable register A
(DTEA) is set to “1,” an IRQ
is served by the CPU.
The interrupt controller holds the IRQ
begins, then clears the IRQ
IRQ
not carried out immediately because the interrupt is masked by bits I2 to I0 in the status register.
On return from the interrupt-handling routine one more instruction is executed, then the
exception-handling sequence for the second IRQ
1
1
0
1
pin. The IRQ
interrupt-handling routine, the request is held, but the IRQ
(Interrupt Request 0): An IRQ
(Interrupt Request 1): An IRQ
0
0
1
interrupt if the TME bit is set to “1” and the WT/IT bit is cleared to “0” in the watchdog
interrupt can be assigned any priority level from 7 to 0 by setting the corresponding
interrupt can be assigned any priority level from 7 (high) to 0 (low) by setting the
0
0
interrupt starts the data transfer controller. Otherwise the interrupt is served by the
start the DTC:
0
to be requested by IRQ
1
interrupt is enabled only when the interrupt request enable 1 bit (IRQ
0
E) in the P1CR is set to “1.” IRQ
1
request. If another interrupt is requested at the IRQ
1
interrupt starts the data transfer controller. Otherwise the interrupt
0
:
1
0
0
0
request until the IRQ
interrupt can be requested by a Low input to the IRQ
interrupt is requested by a High-to-Low transition at the
input:
100
0
0
1
input requests an IRQ
, the T bit of the status register is cleared to “0,”
interrupt is carried out.
0
BSET.B #4, @H'FFFC
BCLR.B #4, @H'FFFC
BSET.B #5, @H'FFFC
OR.B
BSET.B #4, @H'FFF4
1
must be held Low until the CPU
exception-handling sequence
1
exception-handling sequence is
#70, @H'FFF0
0
interrupt if the interrupt
1
pin during the
1
E) in
0
pin