HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 135

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

The data transfer count register is a 16-bit register that counts the number of bytes or words of
data remaining to be transferred. The initial count can be set from 1 to 65,536. A register value of
0 designates an initial count of 65,536.
The data transfer count register is decremented automatically after each byte or word is
transferred. When its value reaches 0, indicating that the designated number of bytes or words
have been transferred, a CPU interrupt is generated with the vector of the interrupt that requested
the data transfer.
6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED)
These four registers designate whether an interrupt starts the DTC. The bits in these registers are
assigned to interrupts as indicated in table 6-3. No bits are assigned to the NMI, FOVI, OVI, and
ERI interrupts, which cannot request data transfers.
Bit
Initial value
Read/Write
Table 6-3 Assignment of Data Transfer Enable Registers
Register Module
DTEA
DTEB
DTEC
DTED
Note: Bits marked “—” should always be cleared to “0.”
If the bit for a certain interrupt is set to “1,” that interrupt is regarded as a request for DTC service.
If the bit is cleared to “0,” the interrupt is regarded as a CPU interrupt request.
Only the 16 interrupts indicated in table 6-3 can request DTC service. DTE bits not assigned to
any interrupt (indicated by “—” in table 6-3) should be left cleared to “0.”
Interrupt Source
IRQ
16-Bit FRT1
16-Bit FRT3
SCI
0
R/W
7
0
Bits 7 to 4
—
—
—
—
7
R/W
6
0
OCIB OCIA
OCIB OCIA
TXI
—
6
R/W
5
0
RXI
—
5
IRQ
ICI
ICI
117
R/W
—
4
4
0
0
Interrupt Source
Module
IRQ
16-Bit FRT2
8-Bit Timer
A/D converter
1
R/W
3
0
Bits 3 to 0
R/W
2
0
—
—
—
—
3
OCIB OCIA
R/W
—
—
—
2
1
0
CMIB CMIA
—
—
1
R/W
0
0
IRQ
ADI
ICI
0
1