HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 16

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

18-2
19-1
19-2
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
C-1 (a) Schematic Diagram of Port 1, Pin P1
C-1 (b) Schematic Diagram of Port 1, Pin P1
C-1 (c) Schematic Diagram of Port 1, Pin P1
C-1 (d) Schematic Diagram of Port 1, Pin P1
C-1 (e) Schematic Diagram of Port 1, Pin P1
C-1 (f) Schematic Diagram of Port 1, Pins P1
C-1 (g) Schematic Diagram of Port 1, Pin P1
C-2
C-3
C-4
C-5
C-6
C-7 (a) Schematic Diagram of Port 7, Pin P7
C-7 (b) Schematic Diagram of Port 7, Pins P7
C-7 (c) Schematic Diagram of Port 7, Pin P7
Hardware Standby Sequence ·························································································313
Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes
(Maximum Synchronization Delay) ··············································································316
Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes
(Minimum Synchronization Delay) ···············································································317
Example of Circuit for Driving a Darlington Transistor Pair ········································322
Example of Circuit for Driving an LED ········································································322
Output Load Circuit ·······································································································325
Basic Bus Cycle (without Wait States) in Expanded Modes ·········································327
Basic Bus Cycle (with 1 Wait State) in Expanded Modes ·············································328
Bus Cycle Synchronized with E Clock ··········································································329
Reset Input Timing ········································································································ 330
Interrupt Input Timing ···································································································330
NMI Pulse Width (for Recovery from Software Standby Mode) ··································330
Bus Release State Timing ······························································································331
E Clock Timing ··············································································································331
Clock Oscillator Stabilization Timing ···········································································332
I/O Port Input/Output Timing ························································································333
Free-Running Timer Input/Output Timing ····································································334
External Clock Input Timing for Free-Running Timers ················································334
8-Bit Timer Output Timing ····························································································335
8-Bit Timer Clock Input Timing ····················································································335
8-Bit Timer Reset Input Timing ····················································································335
PWM Timer Output Timing ··························································································336
SCI Input Clock Timing ································································································336
SCI Input/Output Timing (Synchronous Mode) ····························································336
Schematic Diagram of Port 2 ·························································································413
Schematic Diagram of Port 3 ·························································································414
Schematic Diagram of Port 4 ·························································································415
Schematic Diagram of Port 5 ·························································································416
Schematic Diagram of Port 6 ·························································································417
0
1
2
3
4
7
0
3
5
1
···········································································408
···········································································410
··········································································407
··········································································407
··········································································409
··········································································412
··········································································418
··········································································420
and P1
and P7
6
2
···························································411
···························································419