HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 17

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

C-7 (d) Schematic Diagram of Port 7, Pins P7
C-7 (e) Schematic Diagram of Port 7, Pin P7
C-8
C-9 (a) Schematic Diagram of Port 9, Pins P9
C-9 (b) Schematic Diagram of Port 9, Pins P9
C-9 (c) Schematic Diagram of Port 9, Pin P9
C-9 (d) Schematic Diagram of Port 9, Pin P9
C-9 (e) Schematic Diagram of Port 9, Pin P9
E-1
E-2
E-3
E-4
E-5
E-6
E-7
E-8
E-9
E-10
G-1
G-2
G-3
Tables
1-1
1-2
1-3
1-4
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
Schematic Diagram of Port 8 ·························································································423
Reset during Memory Access (Mode 1) ········································································435
Reset during Memory Access (Mode 1) ········································································436
Reset during Memory Access (Mode 2) ········································································438
Reset during Memory Access (Mode 2) ········································································439
Reset during Memory Access (Mode 3) ········································································441
Reset during Memory Access (Mode 3) ········································································442
Reset during Memory Access (Mode 4) ········································································444
Reset during Memory Access (Mode 4) ········································································445
Reset during Memory Access (Mode 7) ········································································446
Reset during Memory Access (Mode 7) ········································································447
Package Dimensions (CP-84) ························································································451
Package Dimensions (CG-84) ·······················································································451
Package Dimensions (FP-80A) ······················································································452
Features ······························································································································2
Pin Arrangements in Each Operating Mode (CP-84, CG-84) ···········································8
Pin Arrangements in Each Operating Mode (FP-80A) ····················································12
Pin Functions ···················································································································16
Operating Modes ·············································································································23
Mode Control Register ····································································································29
Interrupt Mask Levels ······································································································36
Interrupt Mask Bits after an Interrupt is Accepted ··························································36
Initial Values of Registers ································································································41
General Register Data Formats ························································································42
Data Formats in Memory ·································································································43
Data Formats on the Stack ·······························································································44
Addressing Modes ···········································································································46
Effective Address Calculation ·························································································47
Instruction Classification ·································································································50
Data Transfer Instructions ·······························································································52
Arithmetic Instructions ····································································································53
Logic Operation Instructions ···························································································54
7
5
6
7
4
0
2
, P7
, P9
··········································································422
··········································································426
··········································································427
··········································································428
and P9
5
3
and P7
and P9
1
···························································424
6
4
····················································421
····················································425