HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 256

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
13.3.2 Interval Timer Mode
Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1.
In the interval timer mode, an IRQ
This function can be used to generate IRQ
IRQ
IRQ
determine the source of the interrupt.
0
0
requests from the watchdog timer module have the same vector as IRQ
pin, so the IRQ
H’FF
TCNT
count
H’00
WT/IT = 1
TIME = 1
0
interrupt-handling routine must check the OVF bit in the TCSR to
Figure 13-3 Operation in Watchdog Timer Mode
0
request is generated each time the timer count overflows.
H'00 written
to TCNT
0
requests at regular intervals. See figure 13-4.
241
OVF = 1
NMI requested
0
requests from the
Time t

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