HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 264

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
Bit
Initial value
Read/Write
14.2.5 Serial Mode Register (SMR)—H'FFD8
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H'04 at a reset and in the standby
modes.
Bit 7—Communication Mode (C/A): This bit selects the asynchronous or synchronous
communication mode.
Bit 7
C/A
0
1
Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode. It
is ignored in synchronous mode.
Bit 6
CHR
0
1
Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It
is ignored in synchronous mode.
Bit 5
PE
0
1
Description
Asynchronous communication.
Communication is synchronized with the serial clock.
Description
8 Bits per character.
7 Bits per character.
Description
Transmit: No parity bit is added.
Receive: Parity is not checked.
Transmit: A parity bit is added.
Receive: Parity is not checked.
R/W
C/A
7
0
CHR
R/W
6
0
R/W
PE
5
0
249
R/W
O/E
4
0
STOP
(Initial value)
(Initial value)
(Initial value)
R/W
3
0
2
1
CKS1
R/W
1
0
CKS0
R/W
0
0

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