HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 276

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
Table 14-7 Data Formats in Asynchronous Mode
CHR
0
0
0
0
1
1
1
1
Note:
START: Start bit
2. Clock: In the asynchronous mode it is possible to select either an internal clock created by the
STOP: Stop bit
on-chip baud rate generator, or an external clock input at the SCK pin. Refer to table 14-6.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired baud
rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is
used for clock output, the output clock frequency is equal to the baud rate, and the clock pulse
rises at the center of the transmit data bits. Figure 14-3 shows the phase relationship between
the output clock and transmit data.
SMR Bits
P: Parity bit
PE
0
0
1
1
0
0
1
1
Figure 14-3 Phase Relationship between Clock Output and Transmit Data
Output clock
Transmit data
STOP
0
1
0
1
0
1
0
1
Data Format
START
START
START
START
START
START
START
START
Start bit
8-Bit data
8-Bit data
8-Bit data
8-Bit data
7-Bit data
7-Bit data
7-Bit data
7-Bit data
261
D0
STOP
STOP
P
P
D1
STOP
STOP
STOP
STOP
STOP
P
P
D2
STOP
STOP
STOP
STOP
STOP

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