HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 281

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

When clearing the TDRE bit during data transmission, to assure correct data transfer, do not
clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not
clear the RDRF bit until after reading data from the RDR.
• Data Transmission: The procedure for transmitting data is as follows.
The TDR and TSR function as a double buffer. Continuous data transmission can be achieved
by writing the next transmit data in the TDR and clearing the TDRE bit to 0 while the SCI is
transmitting the current data from the TSR.
If an internal clock source is selected, after transferring the transmit data from the TDR to the
TSR, while transmitting the data from the TSR the SCI also outputs a serial clock signal at the
SCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE =
1), serial clock output is suspended until the next data byte is written in the TDR and the TDRE
bit is cleared to 0. During this interval the TXD pin is held at the value of the last bit
transmitted.
If the external clock source is selected, data transmission is synchronized with the clock signal
input at the SCK pin. When all data bits in the TSR have been transmitted, if the TDR is
empty (TDRE = 1) but external clock pulses continue to arrive, the TXD pin outputs a string of
bits equal to the last bit transmitted.
• Data Reception: The procedure for receiving data is as follows.
(1) Set up the desired transmitting conditions in the SMR, BRR, and SCR.
(2) Set the TE bit in the SCR to 1.
(3) Check that the TDRE bit is set to 1, then write the first byte of transmit data in the TDR.
(4) The first byte of transmit data is transferred from the TDR to the TSR and sent, each bit
(1) Set up the desired receiving conditions in the SMR, BRR, and SCR.
The TXD pin will automatically be switched to output, after which the SCI is ready to
transmit data.
Next clear the TDRE bit to 0.
synchronized with a clock pulse. Bit 0 is sent first.
Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the
TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is
requested.
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