HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 295

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

15.4.1 Single Mode
The single mode is suitable for obtaining a single data value from a single channel. A/D
conversion starts when the ADST bit is set to 1. During the conversion process the ADST bit
remains set to 1. When conversion is completed, the ADST bit is automatically cleared to 0.
When the conversion is completed, the ADF bit is set to 1. If the interrupt enable bit (ADIE) is
also set to 1, an A/D conversion end interrupt (ADI) is requested, so that the converted data can be
processed by an interrupt-handling routine. Alternatively, the interrupt can be served by the data
transfer controller (DTC).
When an A/D interrupt is served by the DTC, the DTC automatically clears the ADF bit to 0.
When an A/D interrupt is served by the CPU, however, the ADF bit remains set until the CPU
reads the ADCSR, then writes a 0 in the ADF bit.
Before selecting the single mode, clock, and analog input channel, software should clear the
ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors.
The following example explains the A/D conversion process in single mode when channel 1
(AN
1. Software clears the ADST bit to 0, then selects the single mode (SCAN = 0) and channel 1
2. The A/D converter samples the AN
3. ADF = 1 and ADIE = 1, so an A/D interrupt is requested.
4. The user-coded A/D interrupt-handling routine is started.
5. The interrupt-handling routine reads the ADCSR value, then writes a 0 in the ADF bit to clear
6. The interrupt-handling routine reads and processes the A/D conversion result.
7. The routine ends.
(CH2 to CH0 = “001”), enables the A/D interrupt request (ADIE = 1), and sets the ADST bit to
1 to start A/D conversion. (Selection of mode, clock channel and setting the ADST bit can be
done at same time.)
Coding Example: (when using the slow clock, CKS = 0)
BCLR #5, @H'FFE8
MOV.B #H'61, @H'FFE8
the end of the conversion process the A/D converter transfers the result to register ADDRB,
sets the ADF bit is set to 1, clears the ADST bit to 0, and halts.
this bit to 0.
1
) is selected. Figure 15-3 shows the corresponding timing chart.
1
input and converts the voltage level to a digital value. At
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