HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 301

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
15.5 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time t
after the ADST bit is set to 1. The sampling process lasts for a time t
. The actual A/D
D
SPL
conversion begins after sampling is completed. Figure 15-5 shows the timing of these steps, and
table 15-4 lists the total conversion times (t
) for the single mode.
CONV
The total conversion time includes t
and t
. The purpose of t
is to synchronize the ADCSR
D
SPL
D
write time with the A/D conversion process, so the length of t
is variable. The total conversion
D
time therefore varies within the minimum to maximum ranges indicated in table 15-4.
In the scan mode, the ranges given in table 15-4 apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = 0) or 128 states
(when CKS = 1).
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