HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 321

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

18.3.3 Exit from Software Standby Mode
The chip can be brought out of the software standby mode by an input at one of three pins: the
NMI pin, RES pin, or STBY pin.
1. Recovery by NMI Pin: When an NMI request signal is received, the clock oscillator begins
2. Recovery by RES Pin: When the RES pin goes Low, the clock oscillator starts. Next, when
3. Recovery by STBY Pin: When STBY the pin goes Low, the chip exits from the software
18.3.4 Sample Application of Software Standby Mode
In this example the chip enters the software standby mode on the falling edge of the NMI input
and recovers from the software standby mode on the rising edge of NMI. Figure 18-1 shows a
timing chart of the transitions.
The nonmaskable interrupt edge bit (NMIEG) in the port 1 control register (P1CR) is originally
cleared to 0, selecting the falling edge as the NMI trigger. After accepting an NMI interrupt in
this condition, software changes the NMIEG bit to 1, sets the SSBY bit to 1, and executes the
SLEEP instruction to enter the software standby mode. The chip recovers from the software
standby mode on the next rising edge at the NMI pin.
operating but clock pulses are supplied only to the watchdog timer (WDT). The watchdog
timer begins counting from H'00 at the rate determined by the clock select bits (CKS2 to
CKS0) in its timer status/control register (TCSR). This rate should be set slow enough to allow
the clock oscillator to stabilize before the count reaches H'FF. When the count overflows from
H'FF to H'00, clock pulses are supplied to the whole chip, the software standby mode ends, and
execution of the NMI interrupt-handling sequence begins.
The clock select bits (CKS2 to CKS0) should be set as follows.
(1) Crystal oscillator: Set CKS2 to CKS0 to a value that makes the watchdog timer interval
(2) External clock input: CKS2 to CKS0 can be set to any value. The minimum value
the RES pin goes High, the CPU begins executing the reset sequence.
When the chip recovers from the software standby mode by a reset, clock pulses are supplied to
the entire chip at once. Be sure to hold the RES pin Low long enough for the clock to stabilize.
standby mode to the hardware standby mode.
equal to or greater than 10ms, which is the clock stabilization time.
(CKS2 = CKS1 = CKS0 = 0) is recommended.
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