HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 323

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
18.4 Hardware Standby Mode
18.4.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin
goes Low.
The hardware standby mode reduces power consumption drastically by halting the CPU, stopping
all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance
state.
The registers of the on-chip supporting modules are reset to their initial values. Only the on-chip
RAM is held unchanged, provided the minimum necessary voltage supply is maintained (at least
2V).*
Notes: 1 The RAME bit in the RAM control register should be cleared to 0 before the STBY
18.4.2 Recovery from Hardware Standby Mode
Recovery from the hardware standby mode requires inputs at both the STBY and RES pins.
When the STBY pin goes High, the clock oscillator begins running. The RES pin should be Low
at this time and should be held Low long enough for the clock to stabilize. When the RES pin
changes from Low to High, the reset sequence is executed and the chip returns to the program
execution state.
Store program code only in on-chip ROM.
Use the hardware standby mode. There is never any additional current in hardware standby
mode.
2 Do not change the inputs at the mode pins (MD2, MD1, MD0) during hardware
pin goes Low, to disable the on-chip RAM during the hardware standby mode.
standby mode. Be particularly careful not to let all three mode inputs go low, since
that would place the chip in PROM mode, causing increased current dissipation.
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