HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 405

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

SSR—Serial Status Register
Bit
Initial value
Read/Write
* Only writing of 0 to clear the flag is enabled.
R/(W)*
TDRE
7
1
Transmit Data Register Empty
0 Cleared from 1 to 0 when:
1 Set to 1 when:
R/(W)*
RDRF
1. CPU reads TDRE = 1, then writes 0 in TDRE.
2. The DTC writes data in TDR.
1. The chip is reset or enters a standby mode.
2. Data is transferred from TDR to TSR.
3. CPU reads TDRE = 0, then clears 0 in TE.
6
0
Receive Data Register Full
0 Cleared from 1 to 0 when:
1 Set to 1 when one character is received normally and
R/(W)*
ORER
1. CPU reads RDRF = 1, then writes 0 in RDRF.
2. RDR is read by the DTC.
3. The chip is reset or enters a standby mode.
transferred from RSR to RDR.
5
0
Overrun Error
0 Cleared from 1 to 0 when:
1 Set to 1 when a framing error occurs (stop bit is 0).
0 Cleared from 1 to 0 when:
1 Set to 1 when an overrun error occurs (next data is
R/(W)*
396
FER
1. CPU reads FER = 1, then writes 0 in FER.
2. The chip is reset or enters a standby mode.
1. CPU reads ORER = 1, then writes 0 in ORER.
2. The chip is reset or enters a standby mode.
completely received while RDRF bit is set to 1).
4
0
0 Cleared from 1 to 0 when:
1 Set to 1 when a parity error occurs (parity of
Framing Error
1. CPU reads PER = 1, then writes 0 in PER.
2. The chip is reset or enters a standby mode.
receive data does not match parity selected by bit).
H'FFDC
R/(W)*
PER
3
0
Parity Error
—
—
2
1
—
—
1
1
SCI
—
—
0
1