HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 449

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
3. Mode 3
Figures E-5 and E-6 show how the pin states change when the RES pin goes Low during external
memory access in mode 3.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D
to D
) is placed in the high-impedance
7
0
state.
The address bus and the signal are initialized 1.5 ø clock periods after the Low state of the RES
pin is sampled. All address bus signals are made Low. The R/W signal is made High.
The clock output pins P1
/ø and P1
/E are initialized 0.5 ø clock periods after the Low state of the
0
1
RES pin is sampled. Both pins are initialized to the output state.
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