HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 47

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

2.3.2 Page 0 Address Allocations
The high and low address areas in page 0 are reserved for registers and vector tables.
Vector Tables: The low address area contains the exception vector table and DTC vector table.
The CPU accesses the exception vector table to obtain the addresses of user-coded exception-
handling routines. The DTC vector table contains pointers to tables of register information used
by the on-chip chip data transfer controller. The size of these tables depends on the CPU
operating mode. Details are given in section 4.1.3, “Exception Factors and Vector Table,” section
5.2.3, “Interrupt Vector Table,” and section 6.3.2, “DTC Vector Table.”
In modes 2 and 4 the vector tables are located in on-chip ROM. In modes 1, 3, and 7 the vector
tables are in external memory.
Register Field: The highest 128 addresses in page 0 (addresses H'FF80 to H'FFFF) belong to
control, status, and data registers used by the I/O ports and on-chip supporting modules. Program
code cannot be located at these addresses.
The CPU accesses addresses in this register field like other addresses in the address space. By
reading and writing at these addresses the CPU controls the on-chip supporting modules and
communicates via the I/O ports. A complete map of the register field is given in appendix B.
On-Chip RAM: One of the control registers in the register field is a RAM control register
(RAMCR) containing a RAM enable bit (RAME) that enables or disables the 1-kbyte on-chip
RAM. When this bit is set to “1” (its default value), addresses H'FFB0 to H'FF7F are located on-
chip. When this bit is cleared to “0,” these addresses are located in external memory and the on-
chip RAM is not used. See section 16, “RAM” for further information.
The RAME bit is bit 7 at address H'FFF9.
Coding Example:
To enable on-chip RAM: BSET.B #7, @H'FFF9
To disable on-chip RAM: BCLR.B #7, @H'FFF9
Note: If on-chip RAM is disabled in the single-chip mode, access to addresses H'FFB0 to H'FF7F
causes an address error.
27