HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 95

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

Notes: The BREQ signal must be held Low until BACK goes Low. If BREQ returns to the High
level before BACK goes Low, the bus release operation may be executed incorrectly.
To leave the bus-released state, the High level at the BREQ pin must be sampled two times. If the
BREQ returns to Low before it is sampled two times, the bus released cycle will not end.
The bus release operation is enabled only when the BRLE bit in the port 1 control register (P1CR)
is set to “1.” When this bit is cleared to “0” (its initial value), the BREQ and BACK pins are used
for general-purpose input and output, as P1
An instruction that sets the BRLE bit is: BSET.B #3, @H'FFFC
Note the following point when using the H8/532’s release function.
If the BREQ signal is asserted and an interrupt is requested simultaneously during execution of the
SLEEP instruction, the BACK signal may fail to be output even though the CPU has released the
bus. This may cause the system to stop for the interval during which BREQ is asserted, with no
device in control of the bus. The interrupts that can cause this state include NMI, IRQ, and all the
interrupts from on-chip supporting modules. When the BREQ signal is deasserted, ending this
state, the CPU takes control of the bus again and resumes normal instruction execution.
The following methods can be used to avoid entering this state.
Method 1: If the BREQ signal is used, do not use the SLEEP instruction.
Method 2: Disable the BREQ signal during execution of the SLEEP instruction. This can be
done by clearing the bus release enable bit (BRLE) in the port 1 control register (P1CR) to 0
immediately bifore executing the SLEEP instruction. (When the BRLE bit is cleared, low inputs
on the BREQ line are not latched on-chip.) Place instructions to set the BRLE bit to 1 at the
beginning of interrupt-handling routines. If the data transfer controller (DTC) is used, place an
instruction to set the BRLE bit immediately after the SLEEP instruction.
If method 2 is used, BREQ inputs will be ignored while the chip is in sleep mode.
(Coding example)
Main Program
BCLR.B
SLEEP
BSET.B
#3, @P1CR
#3, @P1CR
Interrupt-Handling Routine
BSET.B
RTE
3
and P1
76
2
#3, @P1CR
.