74ABT NSC [National Semiconductor], 74ABT Datasheet

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74ABT

Manufacturer Part Number
74ABT
Description
Octal Transparent Latch with TRI-STATE Outputs
Manufacturer
NSC [National Semiconductor]
Datasheet

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C 1995 National Semiconductor Corporation
54ABT 74ABT373
Octal Transparent Latch with TRI-STATE Outputs
General Description
The ’ABT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH When LE is LOW the data that meets the setup
times is latched Data appears on the bus when the Output
Enable (OE) is LOW When OE is HIGH the bus output is in
the high impedance state
Features
Y
Y
Connection Diagrams
TRI-STATE is a registered trademark of National Semiconductor Corporation
for DIP SOIC SSOP and Flatpak
TRI-STATE outputs for bus interfacing
Output sink capability of 64 mA source capability of
32 mA
Note 1 Devices also available in 13 reel Use suffix
Note 2 Contact factory for package availability
74ABT373CSC (Note 1)
74ABT373CSJ (Note 1)
74ABT373CPC
74ABT373CMSA (Note 1)
74ABT373CMTC (Notes 1 2)
Pin Assignment
Commercial
TL F 11547– 1
TL F 11547
54ABT373J 883
54ABT373W 883
54ABT373E 883
Military
e
SCX SJX MSAX and MTCX
Pin Assignment
Package
Number
M20B
M20D
N20B
J20A
MSA20
W20A
E20A
MTC20
for LCC
Y
Y
Y
Y
Y
Y
Y
Y
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF
loads
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down
Nondestructive hot insertion capability
Standard Military Drawing (SMD) 5962-9321801
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead Molded Shrink Small Outline EIAJ Type II
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead Molded Thin Shrink Small Outline JEDEC
TL F 11547 – 2
Package Description
Pin Names
D
LE
OE
O
0
0
– D
–O
7
7
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch
RRD-B30M115 Printed in U S A
(Active HIGH)
(Active LOW)
Outputs
Description
September 1995

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74ABT Summary of contents

Page 1

... Note 1 Devices also available in 13 reel Use suffix Note 2 Contact factory for package availability Connection Diagrams Pin Assignment for DIP SOIC SSOP and Flatpak TL F 11547– 1 ...

Page 2

Functional Description The ’ABT373 contains eight D-type TRI-STATE output buffers When the Latch Enable (LE) in- put is HIGH data on the D inputs enters the latches In this n condition the latches are transparent latch output ...

Page 3

... I DC Electrical Characteristics Symbol Parameter V Input HIGH Voltage IH V Input LOW Voltage IL V Input Clamp Diode Voltage CD V Output HIGH Voltage 54ABT 74ABT OH V Output LOW Voltage OL I Input HIGH Current IH I Input HIGH Current Breakdown Test BVI I Input LOW Current IL V ...

Page 4

... L Min Max 74ABT Units Min Max MHz ...

Page 5

... L 8 Outputs Switching (Note 6) Min Max (Note 7) ns 74ABT 5V– Units C 250 Outputs Switching (Note 4) Max ...

Page 6

Capacitance Symbol Parameter Typ C Input Capacitance (Note 1) Output Capacitance 9 OUT Note measured at frequency f 1 MHz per MIL-STD-883B Method 3012 e OUT t vs Temperature (T ) PLH A C ...

Page 7

LOW vs Temperature (T ) SET Output Switching e L Data 11547– HIGH vs Temperature (T ) HOLD Output Switching e L Data ...

Page 8

Temperature (T ) PHZ Outputs Switching Output TL F 11547– Load Capacitance PLH Output Switching e A Data to Output TL F 11547–27 ...

Page 9

Temperature (T ) PLH Output Switching Output TL F 11547– Temperature (T ) PLH Outputs Switching Output ...

Page 10

AC Loading Includes jig and probe capacitance FIGURE 1 Standard AC Test Load FIGURE 2a Test Input Signal Levels Amplitude Rep Rate MHz 500 FIGURE 2b Test Input Signal Requirements FIGURE ...

Page 11

Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 11547 – 39 ...

Page 12

Physical Dimensions inches (millimeters) 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 12 ...

Page 13

Physical Dimensions inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit JEDEC (S) 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A NS Package Number M20B 13 ...

Page 14

Physical Dimensions inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit EIAJ (SJ) NS Package Number M20D 20-Lead Plastic EIAJ SSOP (MSA) NS Package Number MSA20 14 ...

Page 15

Physical Dimensions inches (millimeters) (Continued) All dimensions are in millimeters 20-Lead Molded Thin Shrink Small Outline Package JEDEC (MTC) 20-Lead Plastic Dual-In-Line Package (P) NS Package Number MTC20 NS Package Number N20B 15 ...

Page 16

Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 ...

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