SSTV16857 FAIRCHILD [Fairchild Semiconductor], SSTV16857 Datasheet

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SSTV16857

Manufacturer Part Number
SSTV16857
Description
14-Bit Register with SSTL-2 Compatible I/O and Reset
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet

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© 2005 Fairchild Semiconductor Corporation
SSTV16857MTD
SSTVN16857MTD
(Preliminary)
SSTV16857 • SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
applications. The SSTVN16857 is a 14-bit register
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MTD48
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500387
Features
Pin Descriptions
Truth Table
L
H
X
n
p
Pin Name
Q
D
RESET
CK
CK
V
V
V
Compliant with DDR-I registered module specifications
Operates at 2.5V
SSTL-2 compatible input and output structure
Differential SSTL-2 compatible clock inputs
Low power mode when device is reset
Industry standard 48 pin TSSOP package
RESET
1
REF
DDQ
DD
Logic LOW
LOW-to-HIGH Clock Transition
HIGH-to-LOW Clock Transition
1
Don’t Care, but not floating unless noted
Logic HIGH
-D
-Q
H
H
H
H
L
14
14
Package Description
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Floating
X or
D
H
X
X
L
n
r
0.2V V
Floating
X or
CK
DD
H
n
n
L
September 2000
Revised June 2005
Floating
www.fairchildsemi.com
X or
CK
H
p
p
L
Q
Q
Q
H
L
L
n
n
n

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SSTV16857 Summary of contents

Page 1

... SSTV16857 • SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset General Description The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin PC1600, 2100, and 2700 DDR DIMM applications. The SSTVN16857 is a 14-bit register designed for use with 184 and 232 pin PC3200 DDR DIMM applications ...

Page 2

... The SSTL-2 data inputs transition based on the value stable system reference used for setting REF REF the trip point of the input buffers of the SSTV16857/ SSTVN16857 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the V signal. REF ...

Page 3

... DC Output Source/Sink Current ( Ground Current DD per Supply Pin (I or Ground Storage Temperature Range (T ) stg DC Electrical Characteristics (SSTV16857) Symbol Parameter V Input LOW Clamp Voltage IKL V Input HIGH Clamp Voltage IKH V AC HIGH Level Input Voltage IH- LOW Level Input Voltage IL-AC V ...

Page 4

... DC Electrical Characteristics (SSTV16857) Symbol Parameter I Dynamic Operating Current DDD Clock Only Dynamic Operating Current per Data Input R Output HIGH On Resistance OH R Output LOW On Resistance Electrical Characteristics (SSTVN16857) Symbol Parameter V Input LOW Clamp Voltage IKL V Input HIGH Clamp Voltage ...

Page 5

... AC Electrical Characteristics (SSTV16857) Symbol Parameter f Maximum Clock Frequency MAX t Pulse Duration, CK, CK HIGH or LOW (Figure Differential Inputs Activation Time, ACT (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) t Differential Inputs De-activation Time, INACT (Note 5) data and clock inputs must be held at valid levels ...

Page 6

Capacitance (Note 15) Symbol Parameter C Data Pin Input Capacitance IN CK Input Capacitance RESET  q Note 15 MHz, Capacitance is characterized but not tested Loading and Waveforms Note: C ...

Page 7

Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to ...

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