DM9620 DAVICOM [Davicom Semiconductor, Inc.], DM9620 Datasheet
DM9620
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DM9620 Summary of contents
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... DAVICOM Semiconductor, Inc. USB2.0 to 10/100M Fast Ethernet Controller Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 DATA SHEET DM9620 USB2.0 to Fast Ethernet Controller Preliminary Version: DM9620-DS-P02 February 20, 2012 1 ...
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... EEPROM & PHY Control Register ( 0BH ) .......................................................................... 21 4.11 EEPROM & PHY Address Register ( 0CH ) ......................................................................... 22 4.12 EEPROM & PHY Data Register ( EE_PHY_L：0DH 4.13 Wake Up Control Register ( 0FH ) ......................................................................................... 22 4.14 Physical Address Register ( 10H~15H )................................................................................. 22 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 USB2.0 to Fast Ethernet Controller CONTENT EE_PHY_H：0EH ) ............ 22 DM9620 ...
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... Transmit Packet Counter/USB Status Register (F2H)............................................................ 28 4.44 USB Control Register (F4H) .................................................................................................. 28 5. EEPROM Format:............................................................................................................................... 29 6. MII Register Description .................................................................................................................... 30 6.1 Basic Mode Control Register (BMCR) – 00H.......................................................................... 31 6.2 Basic Mode Status Register (BMSR) – 01H............................................................................. 32 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 3 ...
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... Ethernet Functional Description ............................................................................................... 52 7.2.1 Serial Management Interface ......................................................................................... 52 7.2.2 100Base-TX Operation .................................................................................................. 52 7.2.3 4B5B Encoder................................................................................................................ 52 7.2.4 Scrambler ....................................................................................................................... 53 7.2.5 Parallel to Serial Converter............................................................................................ 53 7.2.6 NRZ to NRZI Encoder................................................................................................... 53 7.2.7 MLT-3 Converter........................................................................................................... 53 7.2.8 MLT-3 Driver ................................................................................................................ 53 7.2.9 4B5B Code Group.......................................................................................................... 54 7.2.10 100Base-TX Receiver.................................................................................................. 55 7.2.11 Signal Detect................................................................................................................ 55 7.2.12 Adaptive Equalization.................................................................................................. 55 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 4 ...
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... MII TX timing........................................................................................................................... 63 9.5 MII RX timing .......................................................................................................................... 63 9.6 RMII TX timing........................................................................................................................ 64 9.7 RMII RX timing........................................................................................................................ 64 9.8 RevMII TX timing .................................................................................................................... 65 9.9 RevMII RX timing.................................................................................................................... 65 10 Magnetic and Crystal Selection Guide .............................................................................................. 66 10.1 Magnetic Selection Guide....................................................................................................... 66 10.2 Crystal Selection Guide .......................................................................................................... 66 11. Application circuit ............................................................................................................................ 68 12. Package Information ......................................................................................................................... 70 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 5 ...
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... Ordering Information ........................................................................................................................ 71 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 6 ...
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... Ethernet – Speed (10M / 100M) indication Ethernet – Duplex (half / full) indication USB speed indication (full / high speed + traffic modes) Clock Single 25MHz / 30 ppm crystal or oscillator Optional 12MHz crystal for USB Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 7 ...
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... Power Reduced mode (cable detection), and Power Down mode Compatible with 5.0V tolerant I/O 1.1 System Description The DM9620 USB to 10/100Mbps Fast Ethernet controller is a high performance and highly integrated ASIC with embedded SSRAM for packet buffering. It enables low cost and affordable Fast Ethernet network connection to desktop, notebook PC, and embedded system using popular USB ports ...
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... Block Diagram and Block Description USB SIE PHY UTMI Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 EP1 Bulk IN FIFO SRAM Bulk OUT FIFO EP2 Register Control table data EEPROM interface EEPROM USB2.0 to Fast Ethernet Controller RX FIFO MII Ethernet TX MAC PHY FIFO DM9620 ...
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... AVCC3 GND 52 53 RREF VCC33_PLL 57 GNDPLL VCC18 58 VCC3 GND RXGND 64 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 USB2.0 to Fast Ethernet Controller DM9620EP DM9620 32 VCC3 31 RXC 30 EECS 29 EECK 28 EEDIO 27 MDIO 26 MDC 25 RXER 24 RXDV 23 GND 22 RXD0 21 RXD1 20 RXD2 ...
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... Pin Name 26 MDC 27 MDIO 12,13,15,16 TXD[3:0] 11 TXEN 18 TXC 33 CRS 34 COL Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Type Description O,PD MII Serial Management Data Clock I/O MII Serial Management Data O,PD MII Transmit Data 4-bit nibble data outputs (synchronous to the TXC) O,PD MII Transmit Enable I,PD MII Transmit Clock I ...
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... X1_12M 50 X2_12M 3.2.6 LED Interface 38 USB_LED 39 FDX_LED 40 SPD_LED 41 LNK_LED Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 I MII Receive Error I MII Receive Clock I MII Receive Data Valid I MII Receive Data 4-bit nibble data input (synchronous to RXC) Type I/O Data from EEPROM O Clock to EEPROM O ...
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... VBUS input (Connect to USB5V, USB connector) I Tie to high in bus power mode O Issue a wake-up signal when wake-up event happens. Hardware Reset I Active low signal to initiate the DM9620. I Test Mode 2, tie to ground in application. Test Mode 1 0: pins 11-13,15-16,18-22,24-27,33-34 as MII, RMII, Reverse MII I interface 1: pins 11-13,15-16,18-22,24-27,33-34 as GPIO controlled by ...
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... GPIO3_7 3.3 strap pins table 1: pull-high 1K~10K, 0: default floating. Pin No. Pin Name TXD3 12, TXD2 13 TXD1 15 TXD0 16 30 EECS Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 I/O GPIO2_6~7 in GPIO mode I/O GPIO3_0~1 in GPIO mode I/O GPIO3_2 in GPIO mode I GPIO3_3 in GPIO mode I/O I/O GPIO3_4 in GPIO mode I/O GPIO3_5 in GPIO mode I/O ...
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... Vendor Control and Status Register Set The DM9620 implements several control and status registers, which can be accessed by the USB vendor register type commands. All CRs are set to their default values by hardware or software reset unless otherwise specified. Register NCR Network Control Register ...
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... FCOL PHS0,RW 3 FDX PHS0,RW 2:1 LBK PH00,RW Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 E = default value from EEPROM T = default value from strap pin <Access Type> Read only RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write Write only Reserved bits are shaded and should be written with 0. ...
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... PHS0,RO Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Software Reset When write “1” to this bit, DM9620 enters software reset mode and will be automatically cleared after 10us. Write “0” to this bit can end the software reset mode. Description Media Speed Status ...
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... PHS0,RW Pass Runt Packet 1 PRMSC PHS0,RW Promiscuous Mode 0 RXEN PHS0,RW RX Enable Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Reserved Transmit Jabber Disable When set, the transmit Jabber Timer(2048 bytes) is disabled. Otherwise the transmit packet size can more than 2048-byte. Excessive Collision Mode Control : ...
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... RXFU PHS0,RW /C 6:0 ROC PHS0,RW /C Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Runt Frame It is set to indicate the received frame has the size smaller than 64 bytes. Multicast Frame It is set to indicate the received frame has a multicast address. Late Collision Seen It is set to indicate a late collision found during the frame reception. ...
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... PHS3h, RW 3:0 LWOT PHS8h, RW Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern when RX SRAM free space is lower than this threshold value. Default is 3K-byte free space. Please don’t exceed SRAM size. ...
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... ERPRR PH0,RW 1 ERPRW PH0,RW Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Force to TX Pause Packet with Time 0000H,: This bit will be automatically cleared after pause packet transmission completion. Set to TX pause packet with time = 0000H Force to TX Pause Packet with Time FFFFH: This bit will be automatically cleared after pause packet transmission completion ...
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... PAB1 E,RW 7:0 PAB0 E,RW Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 EEPROM Access Status or PHY Access Status When set, it indicates that the EEPROM or PHY access is in progress. Description PHY Address bit [1:0] or EEPROM Word Address[7:6 PHY mode operation , the PHY address bit [4:2] is force to 0. ...
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... Chip Revision Register (2CH) Bit Name Default 7:0 CHIPR 01H,RO Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Multicast Address Byte 7 (1DH) Multicast Address Byte 6 (1CH) Multicast Address Byte 5 (1BH) Multicast Address Byte 4 (1AH) Multicast Address Byte 3 (19H) Multicast Address Byte 2 (18H) ...
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... Bit Name Default 7~3 RESERVED 0,RO 2 UDPCSE HPS0,RW 1 TCPCSE HPS0,RW 0 IPCSE HPS0,RW Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Reserved Late Collision Retry Reserved Reserved TX Inter frame Gap 0XXX: 96-bit 1000: 64-bit 1001: 72-bit 1010: 80-bit 1011: 88-bit 1100: 96-bit 1101: 104-bit 1110:112-bit ...
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... UDP Packet TCP Packet IP Packet Receive Checksum Checking Enable When set, the checksum status will store in packet first byte of status header in RX DM9620 mode. Discard Checksum Error Packet When set, if IP/TCP/UDP checksum field is error, this packet will be discarded. Description External PHY Address Enabled When set in external MII mode, the external PHYceiver address is defined at bit 4~0 ...
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... Bit Name Default 7-0 TX_CTR PS0,RO Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description General Purpose Control 3 Define the input mode (“0”,) or output mode (“1”) of pins GP_GRP3. Where the GP_GRP3 are pins GPIO3 listed in pin description Description General Purpose Register 3 Data When the correspondent bit of General Purpose Control Register 3 is set, i ...
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... RESERVED P,RO 1:0 RESERVED P0,RW Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description USB Data Error Count This counter is increased when there has been data CRC error in USB packet. This counter can be cleared by read if register 5 is “0” write to this register with any data. ...
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... EP3ACK 0,RW 4 EP3NAK 0,RW 3:1 Reserved 0,RW 0 MEMTST 0,RW Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Reserved Reference voltage for USB squelch circuit 000 for Reference voltage = 27.5mV 100 for Reference voltage = 137.5mV (default) 111 for Reference voltage = 220mV Description USB Address Description Reserved USB device address ...
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... String2 address 9 String2 length 9 String3 address 10 String3 length 10 USB control 11 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 offset 0~5 6 byte ethernet address 6-7 Bit 1:0=01: Update vendor ID and product ID Bit 5:2 reserved Bit 7:6=01: Accept setting of WORD7[3:0] Bit 9:8=01: Accept setting of WORD7[6:4] Bit 11:10=01: Accept setting of WORD7[7] Bit 13:12=01: Accept setting of WORD7[8] ...
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... Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Power Isolate Restart Full Coll. Down ...
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... Power down 10 Isolate Restart 9 auto-negotiation Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Default Reset: 1=Software reset 0=Normal operation 0, RW/SC This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed ...
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... Remote fault Auto-negotiatio 3 n ability 2 Link status Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Duplex mode Full duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). With 1,RW auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation Collision test Collision test enabled ...
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... PHY ID Identifier Register #1 (PHYID1) – 02H The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9620. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. ...
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... NP 14 ACK 13 RF Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 0 = Not acknowledged The PHY's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. ...
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... DAVICOM Specified Configuration Register (DSCR) – 10H Bit Bit Name 15 BP_4B5B 14 BP_SCR Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Reserved Write as 0, ignore on read Flow control support Controller chip supports flow control ability by link partner Controller chip doesn’t support flow control ability by link ...
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... SMRST 2 MFPSC 1 SLEEP 0 Reserved Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation Bypass symbol alignment function Receive functions (descrambler, symbol alignment and 0, RW symbol decoding functions) bypassed. Transmit functions ( symbol encoder and scrambler) bypassed ...
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... RESERVED (PHYADR), 8-4 PHYADR[4:0] 3-0 ANMB[3:0] Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Default 100M full duplex operation mode: After auto-negotiation is completed, results will be written to this bit. If this bit means the operation 1 mode is a 100M full duplex 1, RO mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation ...
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... RW 1 PDedo PD10 When selected, the power down value is control by Register 20.0 Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Default Reserved Write as 0, ignore on read Link pulse enable Transmission of link pulses enabled Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation ...
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... MDI/MDIX,RO The polarity of MDI/MDIX value 6 AutoNeg_lpbk 5 Mdix_fix Value 4 Mdix_down 3 MonSel1 2 MonSel0 1 Reserved Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Default 0,RW Vendor test select control 0,RW Vendor test select control 0,RW Force Signal Detect 1: force SD signal OK in 100M 0: normal SD signal. 0,RW Vendor test select control Preamble Saving Control ...
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... Power Saving Control Register (PSCR) – 1DH Bit Bit Name 15-12 RESERVED 11 PREAMBLEX 10 AMPLITUDE 9 TX_PWR 8-0 RESERVED Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Force application. 0,RW Power down control value Decision the value of each field Register 19. 1: power down 0: normal DSP CONTROL For internal testing only Default 0,RO RESERVED 0,RW ...
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... GET_STATUS 10000001B 10000010B 00000000B SET_ADDRESS 00000000B SET_CONFIGURATION 00000000B SET_DESCRIPTOR 00000000B SET_FEATURE 00000001B 00000010B 00000001B SET_INTERFACE 10000010B SYNCH_FRAME Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Setup Stage wValue wIndex Zero Feature Interface Selector Endpoint Zero Zero Descriptor Zero/LID type/index Zero Interface Zero Zero ...
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... WRITE_REGISTER( ) Setup Stage BmReqType bReq Byte 0 Byte 1 40H 01H WRITE1_REGISTER( ) Setup Stage BmReqType bReq Byte 0 Byte 1 40H 03H Data[7:0] Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 WValue WIndex Byte Byte 2 Byte 4 3 RegOffset[7: 00H 00H 0] WValue Byte 2 Byte 3 Byte 4 00H 00H RegOffset[7:0] ...
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... BmReqType BReq Byte 0 Byte 1 Byte 2 40H 05H 00H WRITE1_MEMORY( ) Setup Stage BmReqType Breq Byte 0 Byte 1 Byte 2 40H 07H Data[7:0] Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Wvalue Windex Byte 3 Byte 4 00H 00H MemOff[7:0] WValue Windex Byte 3 Byte 4 00H MemOff[7:0] WValue Windex Byte 3 ...
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... The others : Ethernet Transmit Packet data 3. Endpoint 3 Type: Interrupt In Packet Load: 8-byte When host accessing EP3 interrupt condition, device response NAK. If interrupt condition, device will send content back to host. Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 44 ...
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... Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Description Network status register Reserved Reserved RX status register Received overflow counter register Received packet counter Transmit packet counter Reserved Size Value 1 12H Size of descriptor in bytes 1 01H ...
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... Offset Field 0 bLength 1 bDescriptorType 2 bInterfaceNumber 3 bAlternateSetting 4 bNumEndpoints 5 bInterfaceClass 6 bInterfaceSubClass 7 bInterfaceProtocol 8 iInterface Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Size Value Description 1 09H Size of descriptors 1 02H CONFIGURATION Descriptor Type 2 0027H Total descriptor length 1 01H Number of interfaces 1 01H Value of this configuration 1 00H Index of string descriptor for configuration ...
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... Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Value Description 07H Size of this descriptor 05H ENDPOINT Descriptor Type 81H Address of the endpoint Bit3~0: The endpoint number Bit 6~4: Reserved(0) Bit7 : Direction(Control EP exclude OUT endpoint endpoint ...
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... Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Value Description 07H Size of this descriptor 05H ENDPOINT Descriptor Type 02H Address of the endpoint Bit3~0: The endpoint number Bit 6~4: Reserved(0) Bit7 : Direction(Control EP exclude OUT endpoint endpoint ...
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... String0 Descriptor/Code array Offset Field 0 bLength 1 bDescriptorType 2 wLANGID[1] Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Value Description 07H Size of this descriptor 05H ENDPOINT Descriptor Typr 83H Address of the endpoint Bit3~0: The endpoint number Bit 6~4: Reserved(0) Bit7 : Direction(Control EP exclude OUT endpoint ...
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... Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Value Description Descriptor length In the EEPROM, data is loaded from the low byte address position indexed by the word address position at low byte: 8. 03H STRING Descriptor Type In the EEPROM, data is loaded from the high ...
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... Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Value Description Descriptor length In the EEPROM, data is loaded from the low byte address position indexed by the word address position at low byte: 10. STRING Descriptor Type In the EEPROM, data is loaded from the high ...
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... The block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 MDC PHY MDIO External PHY can be accessed via the MDC, MDIO ...
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... IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9620 includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not require 4B5B conversion. ...
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... Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Meaning 4B code 3210 Data 0 0000 Data 1 0001 Data 2 0010 Data 3 0011 Data 4 0100 Data 5 0101 Data 6 0110 Data 7 0111 Data 8 1000 Data 9 1001 ...
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... USB2.0 to Fast Ethernet Controller conditioning of the received signal independent of the cable length. 7.2.13 MLT-3 to NRZI Decoder The DM9620 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The relationship between NRZI and MLT-3 data is shown in figure 4. 7.2.14 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder ...
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... The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer. 7.2.20 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9620 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then Manchester encoded ...
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... Power pin *2: IO pin 8.1.1 Operating Conditions Symbol Parameter D Supply Voltage VDD P 100BASE-TX D 10BASE-T TX (Power Dissipation) 10BASE-T idle *1 USB suspend mode *1: demo board testing result Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Parameter Min. -0.3 -0.5 -0.3 - Min. 3.135 --- --- --- --- DM9620 USB2.0 to Fast Ethernet Controller Max. ...
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... Differential Rise/Fall Time TR/F t 100TX+/- Differential Rise/Fall Time TM Mismatch t 100TX+/- Differential Output Duty Cycle TDC Distortion T 100TX+/- Differential Output Peak-to-Peak t/T Jitter X 100TX+/- Differential Voltage Overshoot OST Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 USB2.0 to Fast Ethernet Controller Min. Typ. Max. Unit - - 0 ...
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... Oscillator/Crystal Timing ( 25°C ) Symbol Parameter T OSC Clock Cycle CKC T OSC Pulse Width High PWH T OSC Pulse Width Low PWL Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 USB2.0 to Fast Ethernet Controller Min. Typ Max. . 39.9988 40 40.0012 - DM9620 Unit Conditions ns 30ppm ...
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... Power on reset time T2 PWRST# Low Period T3 Strap pin setup time with PWRST# T4 Strap pin hold time with PWRST# T5 PWRST# high to EECS high T6 PWRST# high to EECS burst end Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 USB2.0 to Fast Ethernet Controller Min. Typ. Max. 15 ...
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... EECS EECK EEDIO Symbol T1 EECS Hold Time T2 EECK cycle time T3 EEDIO Hold Time in output state T4 EEDIO Setup Time in input state T5 EEDIO Hold Time in input state Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 T3 Parameter DM9620 USB2.0 to Fast Ethernet Controller Min. Typ. Max. 4.2 5.12 4.2 ...
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... MII Management Timing MDC MDIO (from DM9620) MDIO (to DM9620) Symbol T1 MDC Frequency T2 MDIO by DM9620 Delay Time T3 MDIO by External MII Setup Time T4 MDIO by External MII Hold Time Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 T2 Parameter DM9620 USB2.0 to Fast Ethernet Controller Min. Typ. ...
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... TXE TXD_3~0 Symbol T TXE,TXD_3~0 Delay Time 1 9.5 MII RX timing RXC RXER,RXDV RXD_3~0 Symbol T1 RXDV,RXER, RXD_3~0 Setup Time T2 RXDV, RXER, RXD_3~0 Hold Time Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Parameter T1 Parameter DM9620 USB2.0 to Fast Ethernet Controller T1 Min. Typ. Max Min. Typ. Max. ...
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... RMII TX timing CLK50M TXE TXD_1~0 Symbol T TXE,TXD_1~0 Delay Time 1 9.7 RMII RX timing CLK50M RXDV RXD_1~0 Symbol T1 RXDV,RXD_1~0 Setup Time T2 RXDV,RXD_1~0 Hold Time Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Parameter T1 Parameter DM9620 USB2.0 to Fast Ethernet Controller T1 Min. Typ. Max Min. Typ. Max ...
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... TXC TXE TXD_3~0 Symbol T TXE,TXD_3~0 Delay Time 1 9.9 RevMII RX timing RXC RXDV RXD_3~0 Symbol T1 RXDV, RXD_3~0 Setup Time T2 RXDV, RXD_3~0 Hold Time Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Parameter T1 Parameter DM9620 USB2.0 to Fast Ethernet Controller T1 Min. Typ. Max Min. Typ. ...
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... Equivalent Series Resistance Load Capacitance Case Capacitance Power Dissipation Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 pin-to-pin equivalents. Designers should test and qualify all magnetic specifications before using them in an application. RoHS regulations, please contact with your magnetic vendor, this table only for you ...
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... Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 USB2.0 to Fast Ethernet Controller 25MHz 15pf 15pf GND G ND Figure 10-1 Crystal Circuit Diagram DM9620 67 ...
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... Application circuit DM9620 Reverse MII Block Diagram Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 68 ...
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... DM9620 Reduce MII Block Diagram Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 DM9620 USB2.0 to Fast Ethernet Controller 69 ...
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... θ θ 1 θ 2 θ Dimension D 2. All dimensions are base on metric system. 3. General appearance spec should base on its final visual inspection spec. Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 Dimension in mm Min Nom Max - - 1.60 0.05 - 0.15 1 1.35 1.40 1.45 2 0.17 0.22 0.27 0.17 0.20 0.23 0.09 - ...
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... Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function. Preliminary Version: DM9620 -15-DS-P02 February 20, 2012 application circuits illustrated in this document are for reference purposes only ...