CD4724BC_02 FAIRCHILD [Fairchild Semiconductor], CD4724BC_02 Datasheet

CD4724BC_02

Manufacturer Part Number

CD4724BC_02

Description

8-Bit Addressable Latch

Manufacturer

FAIRCHILD [Fairchild Semiconductor]

Datasheet

1.CD4724BC_02.pdf (7 pages)

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CD4724BCM

CD4724BCN

CD4724BC

8-Bit Addressable Latch

General Description

The CD4724BC is an 8-bit addressable latch with three

address inputs (A0–A2), an active low enable input (E),

active high clear input (C

puts (Q0–Q7).

Data is entered into a particular bit in the latch when that is

addressed by the address inputs and the enable (E) is

LOW. Data entry is inhibited when enable (E) is HIGH.

When clear (C

LOW. When clear (C

channel demultiplexing occurs. The bit that is addressed

has an active output which follows the data input while all

unaddressed bits are held LOW. When operating in the

addressable latch mode (E

than one bit of the address could impose a transient wrong

address. Therefore, this should only be done while in the

memory mode (E

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

) and enable (E) are HIGH, all outputs are

Package Number

HIGH, C

) is HIGH and enable (E) is LOW, the

Top View

M16A

N16E

), a data input (D) and eight out-

LOW).

LOW), changing more

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

DS006003

Features

Truth Table

Wide supply voltage range:

High noise immunity: 0.45 V

Low power TTL compatibility:

Serial to parallel capability

Storage register capability

Random (addressable) data entry

Active high demultiplexing capability

Common active high clear

fan out of 2 driving 74L or 1 driving 74LS

H Follows Data

H Reset to “0”

L Follows Data

L Hold Previous

Package Description

Data

Addressed

Latch

Mode Selection

Holds Previous

Data

Holds Previous

Data

Reset to “0”

Unaddressed

Latch

October 1987

Revised May 2002

3.0V to 15V

(typ.)

www.fairchildsemi.com

Addressable

Latch

Memory

Demultiplexer

Clear

Mode

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CD4724BC_02 Summary of contents

Page 1

CD4724BC 8-Bit Addressable Latch General Description The CD4724BC is an 8-bit addressable latch with three address inputs (A0–A2), an active low enable input (E), active high clear input ( data input (D) and eight out- L puts (Q0–Q7). ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings (Note 2) DC Supply Voltage ( Input Voltage ( Storage Temperature ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( (Soldering, 10 seconds) ...

Page 4

AC Electrical Characteristics pF, R 200k, Input Symbol Parameter t Propagation Delay PHL, tPLH Data to Output Propagation Delay PLH PHL Enable to Output t Propagation Delay ...

Page 5

Switching Time Waveforms 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M16A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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