AT88SA102S_10 ATMEL [ATMEL Corporation], AT88SA102S_10 Datasheet - Page 11

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AT88SA102S_10

Manufacturer Part Number
AT88SA102S_10
Description
Atmel CryptoAuthentication
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
4.1.3. Sleep Flag
4.1.4. Pause State
8584F–SMEM–8/10
Table 4-1.
AT88SA102S always transmits complete blocks to the system, so in the above table the status/error bytes result
in 4-bytes going to the system – count, status/error, CRC x 2.
After receipt of a command block, AT88SA102S will parse the command for errors, a process which takes t
(Refer to Section 4.1.1). After this interval the system can send a Transmit token to AT88SA102S – if there was
an error then AT88SA102S will respond with an error code. If there is no error then AT88SA102S internally
transitions automatically from t
complete.
The sleep flag is used to transition AT88SA102S to the low power state, which causes a complete reset of
AT88SA102S’ internal command engine and input/output buffer. It can be sent to AT88SA102S at any time when
AT88SA102S will accept a flag.
To achieve the specified ISLEEP, Atmel recommends that the input signal be brought below V
asleep. To achieve ISLEEP if the sleep state of the input pin is high, the voltage on the input signal should be
within 0.5V of V
The system must calculate the total time required for all commands to be sent to AT88SA102S during a single
session, including any inter-bit/byte delays. If this total time exceeds t
set of commands, then a Sleep flag, then a Wake token, and finally after the Wake delay the remaining
commands.
The pause state is entered via the PauseLong command and can be exited only when the watchdog timer has
expired and the chip transitions to a sleep state. When in the pause state, the chip ignores all transitions on the
signal pin but does not enter a low power consumption mode.
The pause state provides a mechanism for multiple AT88SA102S chips on the same wire to be selected and to
exchange data with the host microprocessor. The PauseLong command includes an optional address field which
is compared to the values in Fuses 84-87. If the two matches, then the chip enter the pause state, otherwise it
continues to monitor the bus for subsequent commands. The host would selectively put all but one AT88SA102S’
in the pause state before executing the MAC command on the active chip. After the end of the watchdog interval
all the chips will have entered the sleep state and the selection process can be started with a Wake token (which
will then be honored by all chips) and selection of a subsequent chip.
State Description
After Wake, but prior to first
command
After successful command
execution
Execution error
After CRC or other
communications error
Return Codes
CC
to avoid additional leakage on the input circuit of the chip.
Error/Status
PARSE
0xFF
0x11
0x0F
to t
EXEC
Description
Indication that a proper Wake token has been received by Atmel
AT88SA102S
Return bytes per “Output Parameters” in Command section of this
document. In some cases this is a single byte with a value of 0x00 indicating
success. The Transmit flag can be resent to Atmel AT88SA102S repeatedly
if a re-read of the output is necessary.
Command was properly received but could not be executed by Atmel
AT88SA102S. Changes in Atmel AT88SA102S state or the value of the
command bits must happen before it is re-attempted.
Command was NOT properly received by Atmel AT88SA102S and should
be re-issued by the system. No attempt was made to execute the command
and will not respond to any Transmit tokens until both delays are
WATCHDOG
Atmel AT88SA102S
then the system must issue a partial
IL
when the chip is
PARSE
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