AT88SA102S_10 ATMEL [ATMEL Corporation], AT88SA102S_10 Datasheet - Page 13

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AT88SA102S_10

Manufacturer Part Number
AT88SA102S_10
Description
Atmel CryptoAuthentication
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
4.4.2. Synchronization Procedures
4.5.
4.6.
8584F–SMEM–8/10
In order to limit the active current if Atmel
also enabled when AT88SA102S receives a wake-up. If the first token does not come within the t
then AT88SA102S will go back to the sleep mode without performing any operations.
The IO Timeout circuitry is disabled when the chip is busy executing a command.
When the system and the AT88SA102S fall out of synchronization, the system will ultimately end up sending a
Transmit flag which will not generate a response from AT88SA102S. The system should implement its own
timeout which waits for t
system should send a Wake token and after t
resynchronization was successful.
It may be possible that the system does not get the 0x11 code from Atmel
reasons:
1. The system did not wait a full t
2. AT88SA102S went into the sleep mode for some reason while the system was transmitting data. In this case,
3. There is some internal error condition within AT88SA102S which will be automatically reset after a t
Watchdog Failsafe
After the Wake token has been received by AT88SA102S, a watchdog counter is started within the chip. After
t
and/or whether some IO transmission is in progress. There is no way to reset the counter other than to put the
chip to sleep and wake it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various
state machines of AT88SA102S including any IO synchronization issue, power consumption will fall to the low
sleep level automatically.
Byte and Bit Ordering
AT88SA102S is a little-endian chip:
WATCHDOG
• All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the
• Data is transferred to/from AT88SA102S least significant bit first on the bus
• In this document, the most significant bit and/or byte appears towards the left hand side of the page
order received
interpreted the Wake token and Transmit flag as data bits. Recommended resolution is to wait twice the
t
AT88SA102S will interpret the next data bit as a Wake token, but ignore some of the subsequently
transmitted bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be
interpreted as a legal flag, though the following bytes would not be interpreted as a legal command due to an
incorrect count or the lack of a correct CRC. Recommended resolution is to wait the t
issue the Wake token.
interval, see below. There is no way to externally reset AT88SA102S – the system should leave the IO pin
idle for this interval and issue the Wake token.
TIMEOUT
, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command
delay and re-issue the Wake token.
TIMEOUT
during which time AT88SA102S should go to sleep automatically. At this point, the
TIMEOUT
®
delay with the IO signal idle in which case AT88SA102S may have
AT88SA102S is inadvertently awakened, the IO Timeout circuitry is
WLO
+ t
WHI
, a Transmit token. The 0x11 status indicates that the
®
Atmel AT88SA102S
AT88SA102S for one of the following
TIMEOUT
TIMEOUT
delay and re-
WATCHDOG
interval,
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