AT88SA102S_11 ATMEL [ATMEL Corporation], AT88SA102S_11 Datasheet - Page 12

• Manufacturer Part Number: AT88SA102S_11
• Description: Atmel CryptoAuthentication Product Authentication Chip
• Manufacturer: ATMEL [ATMEL Corporation]

5.3.1
5.3.2
5.4
5.5
IO Timeout
After a leading transition for any data token has been received, the AT88SA102S will expect the remaining bits of the token to
be properly received by the chip within the t
(a low pulse exceeding t
The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the
IO Timeout circuitry is enabled until the last expected data bit is received.
Note:
In order to limit the active current if AT88SA102S is inadvertently awakened, the IO timeout circuitry is also enabled when
AT88SA102S receives a wake-up. If the first token does not come within the t
to the sleep mode without performing any operations.
The IO timeout circuitry is disabled when the chip is busy executing a command.
Synchronization Procedures
When the system and the AT88SA102S fall out of synchronization, the system will ultimately end up sending a transmit flag
which will not generate a response from AT88SA102S. The system should implement its own timeout which waits for t
during which time AT88SA102S should go to sleep automatically. At this point, the system should send a Wake token and
after t
It may be possible that the system does not get the 0x11 code from AT88SA102S for one of the following reasons:
1.
2.
3.
Watchdog Failsafe
After the Wake token has been received by AT88SA102S, a watchdog counter is started within the chip. After t
chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO
transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state
machines of AT88SA102S including any IO synchronization issue, power consumption will fall to the low sleep level
automatically.
Byte and Bit Ordering
AT88SA102S is a little-endian chip:
•
•
•
The system did not wait a full t
the Wake token and transmit flag as data bits. Recommended resolution is to wait twice the t
the Wake token.
AT88SA102S went into the sleep mode for some reason while the system was transmitting data. In this case,
AT88SA102S will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted bits
during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag,
though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a
correct CRC. Recommended resolution is to wait the t
There is some internal error condition within AT88SA102S which will be automatically reset after a t
see Section 5.4. There is no way to externally reset AT88SA102S – the system should leave the IO pin idle for this
interval and issue the Wake token.
WLO
All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order
Data is transferred to/from the AT88SA102S least significant bit first on the bus
In this document, the most significant bit and/or byte appears towards the left hand side of the page
received
The timeout counter is reset after every legal token, so the total time to transmit the command may exceed the
+ t
WHI
t
TIMEOUT
, a transmit token. The 0x11 status indicates that the resynchronization was successful.
interval while the time between bits may not.
ZLO
) will cause the chip to enter the sleep state after the t
TIMEOUT
delay with the IO signal idle in which case AT88SA102S may have interpreted
TIMEOUT
interval. Failure to send enough bits or the transmission of an illegal token
TIMEOUT
delay and re-issue the Wake token.
TIMEOUT
Atmel AT88SA102S [DATASHEET]
TIMEOUT
interval, then AT88SA102S will go back
interval.
TIMEOUT
8584G−CRYPTO−9/11
WATCHDOG
delay and re-issue
WATCHDOG
interval,
TIMEOUT
, the
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