AT88SA10HS_10 ATMEL [ATMEL Corporation], AT88SA10HS_10 Datasheet - Page 11

• Manufacturer Part Number: AT88SA10HS_10
• Description: Atmel CryptoAuthentication Host Security Chip
• Manufacturer: ATMEL [ATMEL Corporation]

4.4.2. Synchronization Procedures
4.5.
4.6.
8595F–SMEM–8/10
In order to limit the active current if the Atmel
is also enabled when the AT88SA10HS receives a wake-up. If the first token does not come within the t
interval, the AT88SA10HS will go back to the sleep mode without performing any operations.
The IO Timeout circuitry is disabled when the chip is busy executing a command.
When the system and the AT88SA10HS fall out of synchronization, the system will ultimately end up sending a
Transmit flag which will not generate a response from the AT88SA10HS. The system should implement its own
timeout which waits for t
the system should send a Wake token and after t
resynchronization was successful.
It may be possible that the system does not get the 0x11 code from the AT88SA10HS for one of the following
reasons:
1. The system did not wait a full t
2. The Atmel AT88SA10HS went into the sleep mode for some reason while the system was transmitting data.
3. There are some internal error conditions within the Atmel AT88SA10HS which will be automatically reset after
Watchdog Failsafe
After the Wake token has been received by the AT88SA10HS, a watchdog counter is started within the chip. After
t
and/or whether some IO transmission is in progress. There is no way to reset the counter other than to put the
chip to sleep and wake it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various
state machines of the AT88SA10HS including any IO synchronization issue, power consumption will fall to the low
sleep level automatically.
Byte & Bit Ordering
The AT88SA10HS is a little-endian chip:
WATCHDOG
• All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the
• Data is transferred to/from the Atmel AT88SA10HS least significant bit first on the bus
• In this document, the most significant bit and/or byte appears towards the left hand side of the page
have interpreted the Wake token and Transmit flag as data bits. Recommended resolution is to wait twice the
t
In this case, the Atmel AT88SA10HS will interpret the next data bit as a Wake token, but ignore some of the
subsequently transmitted bits during its wake-up delay. If any bytes are transmitted after the wake-up delay,
they may be interpreted as a legal flag, though the following bytes would not be interpreted as a legal
command due to an incorrect count or the lack of a correct CRC. Recommended resolution is to wait the
t
a t
should leave the IO pin idle for this interval and issue the Wake token.
order received
TIMEOUT
TIMEOUT
WATCHDOG
, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command
delay and re-issue the Wake token.
delay and re-issue the Wake token.
interval, see below. There is no way to externally reset the Atmel AT88SA10HS – the system
TIMEOUT
Atmel AT88SA10HS Host Authentication Chip
during which time the AT88SA10HS should go to sleep automatically. At this point,
TIMEOUT
delay with the IO signal idle in which case the Atmel AT88SA10HS may
®
AT88SA10HS is inadvertently awakened, the IO Timeout circuitry
WLO
+ t
WHI
, a Transmit token. The 0x11 status indicates that the
TIMEOUT
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