AT88SC0104CA-WI ATMEL [ATMEL Corporation], AT88SC0104CA-WI Datasheet - Page 14
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AT88SC0104CA-WI
Manufacturer Part Number
AT88SC0104CA-WI
Description
CryptoMemory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT88SC0104CA-WI.pdf
(20 pages)
Figure 13-1. Synchronous 2-Wire Protocol
13.2
Figure 13-2. Asynchronous T = 0 Protocol (Gemplus Patent)
14. Initial Device Programming
14
Asynchronous T = 0 Protocol
AT88SC0104CA
CLK-SCL
CLK-SCL
I/O-SDA
I/O-SDA
RST
V cc
RST
V cc
Once synchronous mode has been selected, it is not possible to switch to asynchronous mode
without first powering off the device.
Note:
This power-up sequence complies to ISO 7816-3 for a cold reset in smart card applications.
The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory
density within the CryptoMemory family.
Once asynchronous mode has been selected, it is not possible to switch to synchronous mode
without first powering off the device.
Enabling the security features of CryptoMemory requires prior personalization. Personalization
entails setting up of desired access rights by zones, passwords and key values, programming
these values into the configuration memory with verification using simple WRITE and READ
commands, and then blowing fuses to lock this information in place.
Gaining access to the configuration memory requires successful presentation of a secure (or
transport) code. The initial signature of the secure (transport) code for the AT88SC0104CA
V
Set I/O (SDA) in receive mode.
Provide a clock signal to CLK (SCL).
RST goes high after 400 clock cycles.
CC
Five clock pulses must be sent before the first command is issued.
goes high; RST, I/O (SDA) and CLK (SCL) are low.
1
2
3
4
5
ATR
5200AS–CRYPT–7/08