M45PE80-VMN6P NUMONYX [Numonyx B.V], M45PE80-VMN6P Datasheet
M45PE80-VMN6P
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M45PE80-VMN6P Summary of contents
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... Deep Power-down mode 1 µA (typical) ■ More than 100 000 Write cycles ■ More than 20 years’ data retention ■ Packages – ECOPACK® (RoHS compliant) December 2007 VFQFPN8 (MP) 6 × (MLP8) SO8W (MW) 208 mils width SO8N (MN) 150 mils width Rev 9 M45PE80 1/47 www.numonyx.com 1 ...
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... A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Active Power, Stand-by Power and Deep Power-Down modes . . . . . . . . 13 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 2/47 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 M45PE80 ...
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... M45PE80 6.4.2 6.5 Read Data Bytes (READ 6.6 Read Data Bytes at Higher Speed (FAST_READ 6.7 Page Write (PW 6.8 Page Program (PP 6.9 Page Erase (PE 6.10 Sector Erase (SE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down (RDP Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, mechanical data Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4/47 M45PE80 ...
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... M45PE80 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 19 Figure 9 ...
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... Summary description 1 Summary description The M45PE80 Mbit (1 Mbit × 8 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle ...
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... Figure 2. VFQFPN and SO connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Section 11: Package mechanical M45PE80 ...
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... This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is connected them from write, program and erase operations. When Write Protect (W) is connected the first 256 pages of memory behave like the other pages of memory. CC 8/47 , causing the first 256 pages of memory to become read-only by protecting M45PE80 ...
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... M45PE80 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal description 9/47 ...
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... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M45PE80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...
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... M45PE80 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus p MSB ...
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... For optimized timings recommended to use the Page Write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few bytes (see characteristics (50 MHz 12/47 operation)). M45PE80 PW Page Write (PW) and Table 14 ...
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... M45PE80 4.3 A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be: ● when the designer is programming the device for the first time ● ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE80 boasts the following data protection mechanisms: ● Power-On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...
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... M45PE80 5 Memory organization The memory is organized as: ● 4096 pages (256 bytes each). ● 1 048 576 bytes (8 bits each) ● 16 sectors (512 Kbits, 65536 bytes each) Each page can be individually: ● programmed (bits are programmed from ● erased (bits are erased from ● ...
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... Memory organization Figure 5. Block diagram Reset W Control Logic Address Register and Counter 16/47 High Voltage Generator I/O Shift Register 256 Byte Data Buffer 10000h 00000h 256 Bytes (Page Size) X Decoder M45PE80 Status Register FFFFFh First 256 Pages can be made read-only 000FFh AI06812 ...
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... M45PE80 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... Figure 7. Write Disable (WRDI) instruction sequence 18/47 (Figure 6) sets the Write Enable Latch (WEL) bit Instruction D High Impedance Q (Figure 7) resets the Write Enable Latch (WEL) bit Instruction D High Impedance AI02281E AI03750D M45PE80 ...
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... M45PE80 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (40h), and the memory capacity of the device in the second byte (14h) ...
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... Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Q 20/47 Figure Instruction Status Register Out MSB 9. ( WEL Status Register Out MSB M45PE80 b0 (1) WIP 7 AI02031E ...
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... M45PE80 6.5 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
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... BIT ADDRESS Dummy Byte DATA OUT MSB , during the falling edge of Serial Clock (C DATA OUT MSB M45PE80 MSB AI04006 ...
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... M45PE80 6.7 Page Write (PW) The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... Data Byte 2 Data Byte MSB Data Byte MSB Data Byte MSB M45PE80 AI04045 ...
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... M45PE80 6.8 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Address MSB Data Byte MSB Data Byte MSB Data Byte MSB M45PE80 0 AI04044 ...
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... M45PE80 6.9 Page Erase (PE) The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... Figure 15. Sector Erase (SE) instruction sequence Address bits A23 to A20 are Don’t Care. 28/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 15 Instruction 23 22 MSB Bit Address AI03751D M45PE80 ) is ...
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... M45PE80 6.11 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. ...
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... Figure 17. Release from Deep Power-down (RDP) instruction sequence 30/47 Figure 17 Instruction High Impedance Deep Power-down Mode M45PE80 , the device is put in the RDP t RDP Stand-by Mode AI06807 ...
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... M45PE80 7 Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V ● V (min) at Power-up, and then for a further delay ● Power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included ...
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... These parameters are characterized only, over the temperature range –40°C to +85°C. 32/47 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW threshold WI Parameter M45PE80 Read Access allowed Device fully accessible time AI04009C Min. Max. 30 ...
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... M45PE80 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). All usable Status Register bits are 0. 9 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device ...
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... Input capacitance (other pins Sampled only, not 100% tested 34/47 Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC (1) Parameter Test Condition OUT =25°C and a frequency of 20MHz. A M45PE80 Min. Max. Unit 2.7 3.6 V –40 85 °C Min. Max. Unit 0. ...
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... M45PE80 Table 11. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO Standby current I (Standby and Reset CC1 modes) Deep Power-down I CC2 current Operating current I CC3 (FAST_READ) I Operating current (PW) CC4 I Operating current (SE) CC5 V Input low voltage IL V Input high voltage ...
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... Page Erase Cycle Time Sector Erase Cycle Time C Table 8 and Table 9 Min. Typ. Max. D. 200 100 10.2+ n*0.8/256 1.2 5 0.4+ n*0.8/256 M45PE80 Unit MHz MHz μs μ ...
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... M45PE80 Table 13. AC characteristics (33 MHz operation) 33 MHz only available for products marked since week 40 of 2005 Symbol Alt. Clock frequency for the following instructions: FAST_READ, PW, PP, PE SE, DP, RDID, RDP, WREN, WRDI, RDSR f Clock frequency for READ instructions R ( Clock High time ...
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... Table 8 Parameter (4) (peak to peak) C (2) and Table 9 Min. Typ. Max. D. 100 0 50 100 11 0.8 int(n/8) × 0.025 10 1 M45PE80 Unit 50 MHz 33 MHz µs 30 µs 10 µs 3 µ ...
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... M45PE80 Figure 20. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 21. Write Protect setup and hold timing W tWHSL High Impedance Q Figure 22. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tSLCH tCHSH tCHDX tCLCH MSB IN tCLQV DC and AC parameters tSHSL tSHCH tCHCL LSB IN ...
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... Under completion of an Erase or Program cycle of a PW, PP, PE, SE operation Device deselected (S High) and in Standby mode tSHRH tRLRH Table 8 and Table 9 Min. Typ (1) Table 8 and Table 9 Min. Typ. (2) : tRHSL AI06808 M45PE80 Max. Unit µs ns Max. Unit 30 µs 300 µs 0 µs ...
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... M45PE80 11 Package mechanical Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 × 5 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 17. VFQFPN8 (MLP8)8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 × ...
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... Typ Min Max 2.50 0.00 0.25 1.51 2.00 0.40 0.35 0.51 0.20 0.10 0.35 0.10 6.05 5.02 6.22 7.62 8.89 1.27 – – 0° 10° 0.50 0. inches Typ Min 0.000 0.059 0.016 0.014 0.008 0.004 0.198 0.300 0.050 – 0° 0.020 8 M45PE80 6L_ME Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 – 10° 0.031 ...
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... M45PE80 Figure 26. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data Symbol ccc ccc ...
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... Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 44/47 M45PE80 – (1) M45PE80 ...
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... M45PE80 13 Reference ● AN1995: Serial Flash Memory Device Marking. 14 Revision history Table 21. Document revision history Date Version 10-Feb-2003 02-Apr-2003 08-Apr-2003 05-May-2003 04-Jun-2003 26-Nov-2003 23-Jan-2004 28-May-2004 10-May-2005 4-Oct-2005 14-Feb-2006 1.0 Document written 1.1 VFQFPN8 (MLP) package added 1.2 Document promoted to Product Preview 1.3 Document promoted to Preliminary Data Description corrected of entering Hardware Protected mode (W must be 1 ...
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... SO8N package added (T9HX technology only), SO8W and VFQFPN8 package specifications updated (see 9 Applied Numonyx branding. Changes Table 14: AC characteristics (50 MHz updated. V supply voltage and CC modified and Section 7: Power-up and added in Table 7: Absolute maximum and Table 16: Timings after a Reset Low Section 11: Package mechanical). M45PE80 V ground SS ...
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... M45PE80 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...