NAND01G-N STMICROELECTRONICS [STMicroelectronics], NAND01G-N Datasheet
NAND01G-N
Related parts for NAND01G-N
NAND01G-N Summary of contents
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... Quad internal Banks controlled by BA0 and BA1 Wrap sequence: Sequential/Interleaved Automatic and Controlled Precharge Auto Refresh and Self Refresh 8,192 Refresh Cycles/64ms Burst Termination by Burst Stop command and Precharge Command Rev1.0 NAND01G-N PRELIMINARY DATA FBGA TFBGA107 10 1.2mm TFBGA149 10 x 13.5 x 1.2mm 1/23 www.st.com 2 ...
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... Table 1. Product List Reference Part Number NAND01GR3N6 NAND01G-N NAND01GR4N5 1. SDR = Single Data Rate; DDR = Double Data Rate. 2/23 NAND Product LPSDRAM Product 1Gbit 1.8V (x8) SDR 512Mbit (x16) 1.8V, 133MHz 1Gbit 1.8V (x16) DDR 512Mbit (x16) 1.8V, 133 MHz Rev1.0 NAND01G-N (1) Package TFBGA107 TFBGA149 ...
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... NAND01G-N Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 NAND Flash component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LPSDRAM component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Flash memory Inputs/Outputs (I/O0-I/O7 2.2 Flash memory Inputs/Outputs (I/O8-I/O15 2.3 Flash memory Address Latch Enable (AL 2.4 Flash memory Command Latch Enable (CL 2.5 Flash memory Chip Enable (EF 2.6 Flash memory Read Enable ( ...
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... Contents 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4/23 Rev1.0 NAND01G-N ...
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... NAND01G-N List of tables Table 1. Product List Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data . . . . . . 19 Table 5. TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data . . . . . . 20 Table 6. Ordering Information Scheme Table 7. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Rev1 ...
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... TFBGA107 connections, x16 Bus Width (Top view through package Figure 3. TFBGA149 Connections (Top view through package Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline . . . . . . 19 Figure 6. TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, package outline . . . . . . 20 6/23 Rev1.0 NAND01G-N ...
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... NAND01G-N 1 Summary description The NAND01G family that combine two memory devices in a Multi-Chip Package Gbit NAND Flash memory and 512 Mbit LPSDRAM with 2Kbyte Pages. The NAND Flash memory and LPSDRAM components have separate power supplies and grounds. They also have separate control, address and input/output signals, which allows simultaneous access to both devices at any moment ...
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... Summary description Figure 1. Logic Diagram 1. Available on NAND01GR4N5 only. 8/ DDQD DDD DDF 13 A0-A12 2 BA0-BA1 NAND01G ( RAS CAS DQM0 DQM1 SSQD SSD SSF Rev1.0 NAND01G-N I/O8-I/O15, x16 (1) I/O0-I/O7, x8/x16 DQ0-DQ15 UDQS-LDQS (1) RB AI10142d ...
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... NAND01G-N Table 2. Signal Names I/O0-I/O7 I/O8-I/O15 DDF V SSF A0-A12 BA0-BA1 DQ0-DQ15 (1) UDQS-LDQS K ( RAS CAS DQM0 DQM1 V DDD V DDQD V SSD V SSQD Available on NAND01GR4N5 only. NAND Flash memory Data Input/Outputs for x8 and x16 devices ...
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... DQ7 DQM0 DQM1 DQ8 I/O0 I/O2 DQ9 DQ10 NC NC DQ11 DQ12 I/O1 I/O3 DQ13 DQ14 SSD V SSF DQ15 V DDF Rev1.0 NAND01G A10 BA0 BA1 RAS SSD CAS DDD A12 KE A11 I/O4 I/O6 A6 ...
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... NAND01G-N Figure 3. TFBGA149 Connections (Top view through package SSF DDF ...
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... When Chip Enable is low, V memory device is selected. If Chip Enable goes high, v busy, the device remains selected and does not go into standby mode. 12/23 Table 2, for a brief overview of the signals connected to this ) F , while the NAND Flash memory is IH Rev1.0 NAND01G-N , the NAND Flash IL ...
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... NAND01G-N 2.6 Flash memory Read Enable (R) The NAND Flash memory Read Enable pin, R, controls the sequential data output during Read operations. The falling edge of R also increments the internal column address counter by one. 2.7 Flash memory Write Enable (W The NAND Flash memory Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches ...
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... The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and BA1-BA0, to select the starting address location prior to a Read or Write. 2.18 LPSDRAM Write Enable (W The LPSDRAM Write Enable input, W, controls writing to the LPSDRAM. 14/23 , when selecting the addresses When High, V the device is not selected Rev1.0 NAND01G-N , the IL ...
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... NAND01G-N 2.19 LPSDRAM Clock Input (K) The Clock signal used to clock the Read and Write cycles on the LPSDRAM. During normal operation, the Clock Enable pin, KE, is High, V suspended to switch the device to the Self-Refresh, Power-Down or Deep Power-Down mode by driving KE Low, V 2.20 LPSDRAM Clock Input (K) The Clock signal only available on the DDR LPSDRAM ...
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... LPSDRAM V Ground the reference for the core power supply for the LPSDRAM. It must be SSD, connected to the system ground. 16/23 supply voltage DDQD . V can be tied to V DDD DDQD ground SSD Rev1.0 NAND01G-N or can use a separate DDD and V together to avoid certain DDD DDQD ...
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... NAND01G-N 3 Functional description The NAND Flash memory and LPSDRAM components have separate power supplies and grounds. They also have separate control signals, addresses and data input/outputs, which allows simultaneous access to both devices at any moment. Figure 4. Functional Block Diagram 1. Available on Root Part Number 2 only. ...
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... NAND Flash Supply Voltage DDF LPSDRAM Supply Voltage DDD DDQD LPSDRAM Short Circuit I OS Output Current LPSDRAM Power PD Dissipation 1. TBD stands for ‘To Be Determined’. 18/23 Parameter (1) 1.8V 1.8V 1.8V 1.8V Rev1.0 NAND01G-N Value Unit Min Max -30 85 °C TBD TBD °C -55 125 °C -0.6 2.7 V -1.0 2.6 V -0.6 2 ...
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... NAND01G-N 5 Package mechanical Figure 5. TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline BALL "B1" Table 4. TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data Symbol Typ 0.80 b 0.45 D 10.50 D1 7.20 ddd E 13.00 E1 10.40 e 0.80 FD 1.65 FE 1.30 SD 0. ...
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... Rev1.0 NAND01G-N ddd BGA-Z78 inches Typ Min Max 0.0472 0.0098 0.0157 0.0197 0.3898 0.3976 0.0039 0.5276 0.5354 – – – – – ...
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... NAND01G-N 6 Part numbering Table 6. Ordering Information Scheme Example: Device Type NAND Flash Memory NAND Flash Density 01G = 1Gb NAND Flash Operating Voltage R = 1.7V to 1.95V Bus Width x16 Family Identifier N = 2112 Byte Page NAND Flash + LPSDRAM Device Options 5 = DDR LPSDRAM 512Mbit (x16), 133 Mhz, BGA149 ...
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... Section 2: Signals description added. 256Mb LPSDRAM removed. LFBGA107 ( 1.4mm) and LFBGA149 (10 x 13.5 x 1.4mm) replaced by TFBGA107 (10.5x13x1.2mm) and TFBGA149 (10x13.5x1.2mm), respectively. Rev1.0 NAND01G-N Revision Details Table 1: Product List modified. and Figure 1: Logic Diagram and Section 3: Functional description added ...
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... NAND01G-N Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...