NAND02G-B2D NUMONYX [Numonyx B.V], NAND02G-B2D Datasheet - Page 36

• Manufacturer Part Number: NAND02G-B2D
• Description: 2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.11.2
6.11.3
Note:
6.11.4
6.11.5
Table 12.
1. Only valid for cache operations.
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SR4, SR3,
SR2, SR1
SR7
SR6
SR5
SR0
Bit
P/E/R controller and cache ready/busy bit (SR6)
Status register bit SR6 has two different functions depending on the current operation.
During cache operations, SR6 acts as a Cache Ready/Busy bit, which indicates whether the
Cache register is ready to accept new data. When SR6 is set to '0', the Cache register is
busy, and when SR6 is set to '1', the Cache register is ready to accept new data.
During all other operations, SR6 acts as a P/E/R controller bit, which indicates whether the
P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
P/E/R controller bit (SR5)
The Program/Erase/Read controller bit indicates whether the P/E/R controller is active or
inactive during cache operations. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
This bit is only valid for cache operations.
Error bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R controller. The
Error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the Error bit is set to ‘0’ the operation has completed successfully.
SR4, SR3, SR2 and SR1 are reserved
Status register bits
Program/Erase/Read
Program/Erase/Read
Write protection
Generic error
controller
Reserved
controller
Name
(1)
Logic level
Don’t care
‘1’
‘0’
'1'
'0'
'1'
'0'
'1'
'0'
Not protected
Protected
P/E/R controller inactive, device ready
P/E/R controller active, device busy
P/E/R controller inactive, device ready
P/E/R controller active, device busy
Error – operation failed
No error – operation successful
Definition
NAND02G-B2D