M58BW016DB7T3FF NUMONYX [Numonyx B.V], M58BW016DB7T3FF Datasheet - Page 18

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M58BW016DB7T3FF

Manufacturer Part Number
M58BW016DB7T3FF
Description
16 Mbit (512 Kbit x 32, boot block, burst) 3 V supply Flash memories
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
Bus operations
3
3.1
3.1.1
3.1.2
18/70
Bus operations
Each bus operation that controls the memory is described in this section, see
Table 5
the burst configuration register; the bits in this register are described at the end of this
section.
On power-up or after a hardware reset the memory defaults to asynchronous bus read and
asynchronous bus write, no other bus operation can be performed until the burst control
register has been configured.
The electronic signature, CFI or status register will be read in asynchronous mode
regardless of the burst control register settings.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
Asynchronous bus operations
For asynchronous bus operations refer to
Asynchronous bus read
Asynchronous bus read operations read from the memory cells, or specific registers
(electronic signature, status register, CFI and burst configuration register) in the command
interface. A valid bus operation involves setting the desired address on the address inputs,
applying a Low signal, V
Output Disable High, V
Asynchronous bus read AC
characteristics, for details of when the output becomes valid.
Asynchronous read is the default read mode which the device enters on power-up or on
return from reset/power-down.
Asynchronous latch controlled bus read
Asynchronous latch controlled bus read operations read from the memory cells or specific
registers in the command interface. The address is latched in the memory before the value
is output on the data bus, allowing the address to change during the cycle without affecting
the address that the memory uses.
A valid bus operation involves setting the desired address on the address inputs, setting
Chip Enable and Latch Enable Low, V
latched on the rising edge of Latch Enable. Once latched, the address inputs can change.
Set Output Enable Low, V
Asynchronous latch controlled bus read AC
controlled bus read AC
Note that, since the Latch Enable input is transparent when set Low, V
read operations can be performed when the memory is configured for asynchronous latch
enable bus operations by holding Latch Enable Low, V
and
Table 6
Bus operations, for a summary. The bus operation is selected through
IH
characteristics, for details on when the output becomes valid.
IL
. The data inputs/outputs will output the value, see
, to Chip Enable and Output Enable and keeping Write Enable and
IL
, to read the data on the data inputs/outputs; see
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
waveforms, and
IL
and keeping Write Enable High, V
Table 4
waveforms, and
Table 16: Asynchronous bus read AC
together with the following text.
IL
throughout the bus operation.
Table 17: Asynchronous latch
IL
, asynchronous bus
IH
; the address is
Figure 8:
Figure 9:
Table
4,

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