M58BW016DB7T3FF NUMONYX [Numonyx B.V], M58BW016DB7T3FF Datasheet - Page 22

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M58BW016DB7T3FF

Manufacturer Part Number
M58BW016DB7T3FF
Description
16 Mbit (512 Kbit x 32, boot block, burst) 3 V supply Flash memories
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
Bus operations
3.2.2
22/70
Valid Data Ready may be configured (by bit M8 of burst configuration register) to be valid
immediately at the valid clock edge or one data cycle before the valid clock edge.
Synchronous burst read will be suspended if Burst Address Advance, B, goes High, V
If Output Enable is at V
If Output Enable, G, is at V
Advance, B, is at V
K valid edge.
The synchronous burst read timing diagrams and AC characteristics are described in the AC
and DC parameters section. See
Table
Synchronous burst read suspend
During a synchronous burst read operation it is possible to suspend the operation, freeing
the data bus for other higher priority devices.
A valid synchronous burst read operation is suspended when both Output Enable and Burst
Address Advance are High, V
burst counter and the Output Enable going High, V
synchronous burst read operation can be resumed by setting Output Enable Low.
Table 6.
1. X = don't care, V
2. M15 = 0, bit M15 is in the burst configuration register.
3. T = transition, see M6 in the burst configuration register for details on the active edge of K.
Synchronous
burst read
Bus operation
20.
Synchronous burst read bus operations
IL
Address Latch
Read
Read Suspend
Read Resume
Burst Address
Advance
Read Abort, E
Read Abort, RP
or V
IL
the internal Burst Address counter is incremented at each Burst Clock
IH
.
IL
and Output Disable is at V
Step
IH
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
or Output Disable, GD, is at V
IH
. The Burst Address Advance going High, V
Figure
V
V
V
V
V
V
13,
E
X
IH
IL
IL
IL
IL
IL
Figure
V
V
V
V
V
G
X
X
IH
IH
IH
IL
IL
GD RP K
V
V
IH
X
X
X
X
X
14,
IH
IH
IH
, inhibits the data outputs. The
, the last data is still valid.
Figure 15
V
V
V
V
V
V
V
(1)(2)
IH
IH
IH
IH
IH
IH
IL
IL
, but the Burst Address
T
T
X
T
T
X
X
(3)
and
V
V
V
V
V
L
X
X
IH
IH
IH
IH
IL
Figure
V
V
V
V
B
X
X
X
IH
IL
IL
IL
IH
16, and
, stops the
Address input
Data output
Data output
DQ0-DQ31
A0-A18
High-Z
High-Z
High-Z
High-Z
IH
.

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