M58BW032BB45T3T STMICROELECTRONICS [STMicroelectronics], M58BW032BB45T3T Datasheet - Page 14

• Manufacturer Part Number: M58BW032BB45T3T
• Description: 32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Enable Controlled Read or Write or Synchronous
Burst Read operations. In Synchronous Burst
Read operations the address is latched on the ac-
tive edge of the Clock when Latch Enable is Low,
V
without affecting the address used by the memory.
When Latch Enable is Low, V
parent. Latch Enable, L, can remain at V
Asynchronous Random Read and Write opera-
tions.
Burst Clock (K). The Burst Clock, K, is used to
synchronize the memory with the external bus dur-
ing Synchronous Burst Read operations. Bus sig-
nals are latched on the active edge of the Clock. In
Synchronous Burst Read mode the address is
latched on the first rising clock edge when Latch
Enable is Low, V
Enable, whichever occurs first.
During Asynchronous bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during Synchro-
nous Burst Read operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X-latency
time has expired. If Burst Address Advance is
Low, V
Burst Address Advance is High, V
address counter does not change; the same data
remains on the Data Inputs/Outputs and Burst Ad-
dress Advance is not sampled until the Y-latency
expires.
The Burst Address Advance, B, may be tied to V
Valid Data Ready (R). The Valid Data Ready
output, R, can be used during Synchronous Burst
Read operations to identify if the memory is ready
to output data or not. The Valid Data Ready output
can be configured to be active on the clock edge
of the invalid data read cycle or one cycle before.
Valid Data Ready, at V
14/60
IL
. Once latched, the addresses may change
IL
, the internal address counter advances. If
IL
, or on the rising edge of Latch
IH
, indicates that new data
IL
, the latch is trans-
IH
, the internal
IL
for
IL
.
is or will be available. When Valid Data Ready is
Low, V
Write Protect (WP). The Write Protect, WP, pro-
vides protection against program or erase opera-
tions. When Write Protect, WP, is at V
protection status that has been configured in the
Block Protection Configuration Register is activat-
ed. Program and erase operations to protected
blocks are disabled. When Write Protect WP is at
V
no other protection is used.
Supply Voltage (V
is the core power supply. All internal circuits draw
their current from the V
gram/Erase Controller.
Output Supply Voltage (V
ply Voltage, V
for all operations (Read, Program and Erase) used
for DQ0-DQ31 when used as outputs.
Input Supply Voltage (V
ply Voltage, V
signal. Input signals are: K, B, L, W, GD, G, E, A0-
A18 and D0-D31, when used as inputs.
Ground (V
reference for the internal supply voltage V
Ground V
input supplies V
connect V
Note: A 0.1 F capacitor should be connected
between the Supply Voltages, V
V
ple the current surges from the power supply.
The PCB track widths must be sufficient to car-
ry the currents required during all operations
of the parts, see
for maximum current supply requirements.
Don’t Use (DU). This pin should not be used as it
is internally connected. Its voltage level can be be-
tween V
Not Connected (NC). This pin is not physically
connected to the device.
DDIN
IH
all the blocks can be programmed or erased, if
and the Grounds, V
IL
SS
, the previous data outputs remain active.
SSQ
SS
SS
and V
and V
DDQ
DDIN
and V
is the reference for the output and
DDQ,
DDQ
, is the output buffer power supply
, is the power supply for all input
Table 15., DC
SSQ
DD
SSQ
and V
or leave it unconnected.
). The Supply Voltage, V
together.
DD
). The Ground V
DDQIN
SS
DDQIN
pin, including the Pro-
DDQ
and V
). The Input Sup-
). The Output Sup-
Characteristics,
. It is essential to
DD
SSQ
, V
to decou-
SS
DDQ
DD
IL
is the
. The
, the
and
DD
,