M58BW032BB45T3T STMICROELECTRONICS [STMicroelectronics], M58BW032BB45T3T Datasheet - Page 17

• Manufacturer Part Number: M58BW032BB45T3T
• Description: 32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Synchronous Bus Operations
For synchronous bus operations refer to Table
together with the following text.
Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external ref-
erence clock. The valid edge of the Clock signal is
the rising edge. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion. Refer to Figure
synchronous burst operations.
In continuous burst read, one burst read operation
can access the entire memory sequentially by
keeping the Burst Address Advance B at V
the appropriate number of clock cycles. At the end
of the memory address space the burst read re-
starts from the beginning at address 000000h.
A valid Synchronous Burst Read operation begins
when the Burst Clock is active and Chip Enable
and Latch Enable are Low, V
dress is latched and loaded into the internal Burst
Address Counter on the valid Burst Clock K edge
or on the rising edge of Latch Enable, whichever
occurs first.
After an initial memory latency time, the memory
outputs data each clock cycle (or two clock cycles
depending on the value of M9). The Burst Address
Advance B input controls the memory burst output.
The second burst output is on the next clock valid
edge after the Burst Address Advance B has been
pulled Low.
Valid Data Ready, R, monitors if the memory burst
boundary is exceeded and the Burst Controller of
the microprocessor needs to insert wait states.
Table 5. Synchronous Burst Read Bus Operations
Note: 1. X = Don't Care, V
Synchronous Burst
Read
Bus Operation
2. M15 = 0, Bit M15 is in the Burst Configuration Register.
3. R= Rising Edge.
(2)
IL
or V
Address Latch
Read
Read Suspend
Read Resume
Burst Address Advance
Read Abort, E
Read Abort, RP
IH
.
5
IL
. The burst start ad-
for examples of
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Step
IL
for
5
V
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IL
When Valid Data Ready is Low on the rising clock
edge, no new data is available and the memory
does not increment the internal address counter at
the active clock edge even if Burst Address Ad-
vance, B, is Low.
Valid Data Ready may be configured (by bit M8 of
Burst Configuration Register) to be valid immedi-
ately at the rising clock edge or one data cycle be-
fore the rising clock edge.
Synchronous Burst Read will be suspended if
Burst Address Advance, B, goes High, V
If Output Enable is at V
V
If Output Enable, G, is at V
GD, is at V
at V
mented at each Burst Clock K rising edge.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 13, 14,
15
Synchronous Burst Read Suspend. During
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is sus-
pended when both Output Enable and Burst Ad-
dress Advance are High, V
Advance going High, V
and the Output Enable going High, V
data outputs. The Synchronous Burst Read oper-
ation can be resumed by setting Output Enable
Low.
IH
V
V
V
V
V
G
X
X
IH
IH
IH
IL
IL
and 16, and Table 20.
, the last data is still valid.
IL
the internal Burst Address Counter is incre-
GD
V
V
X
X
X
X
X
IH
IH
IL
, but the Burst Address Advance, B, is
V
V
V
V
V
V
RP
V
IH
IH
IH
IH
IH
IH
IL
R
R
R
R
K
X
X
X
(3)
(3)
(3)
(3)
IL
IH
V
V
V
V
V
, stops the burst counter
X
X
and Output Disable is at
L
IH
IH
IH
IH
IL
IH
IH
. The Burst Address
V
V
V
V
or Output Disable,
B
X
X
X
IH
IL
IL
IL
IH
Address Input
Data Output
Data Output
DQ0-DQ31
, inhibits the
A0-A19
High Z
High Z
High Z
High Z
IH
.
17/60
a