M58BW032BB45T3T STMICROELECTRONICS [STMicroelectronics], M58BW032BB45T3T Datasheet - Page 24

• Manufacturer Part Number: M58BW032BB45T3T
• Description: 32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
The Status Register should be cleared before re-
issuing the command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Erase operation. The com-
mand will only be accepted during a Program or
Erase operation. It can be issued at any time dur-
ing a program or erase operation. The command
is ignored if the device is already in suspend
mode.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 10.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Program, the Write
to Buffer and Program, the Set/Clear Block Protec-
tion Configuration Register and the Program Sus-
pend commands will also be accepted. When a
program operation is completed inside a Block
Erase Suspend the Read Memory Array command
must be issued to reset the device in Read mode,
then the Erase Resume command can be issued
to complete the whole sequence. Only the blocks
not being erased may be read or programmed cor-
rectly.
See Appendix A,
Resume Flowchart and Pseudo
23., Erase Suspend & Resume Flowchart and
Pseudo
the Program/Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
24/60
Code, for suggested flowcharts on using
Figure 21., Program Suspend &
Code, and
Figure
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command.
See Appendix A,
Resume Flowchart and Pseudo
23., Erase Suspend & Resume Flowchart and
Pseudo
the Program/Erase Suspend command.
Set Burst Configuration Register Command.
The Set Burst Configuration Register command is
used to write a new value to the Burst Configura-
tion Register which defines the burst length, type,
X and Y latencies, Synchronous/Asynchronous
Read mode.
Two Bus Write cycles are required to issue the Set
Burst Configuration Register command. The first
cycle writes the setup command. The second cy-
cle writes the address where the new Burst Con-
figuration Register content is to be written, and
confirms the command. If the command is not con-
firmed, the sequence is aborted and the device
outputs the Status Register with bits 4 and 5 set to
‘1’. Once the command is issued the memory re-
turns to Read mode as if a Read Memory Array
command had been issued.
The value for the Burst Configuration Register is
always presented on A0-A15. M0 is on A0, M1 on
A1, etc.; the other address bits are ignored.
Tuning Protection Unlock Command
The Tuning Protection Unlock command unlocks
the tuning protected blocks by writing the 64bit
Tuning Protection Code (M58BW032B only). After
a reset or power-up the blocks are locked and so
a Tuning Protection Unlock command must be is-
sued to allow program or erase operations on tun-
ing protected block or to program a new Tuning
Protection Code. Read operations output the Sta-
tus Register content after the unlock operation has
started.
The Tuning Protection Code is composed of 64
bits, but the data bus is 32 bits wide so four (2 x 2)
write cycles are required to unlock the device.
Bit 7 of the Status Register should now be
checked to verify that the device has successfully
stored the first part of the code in the internal reg-
ister. If b7 = ‘1’, the device is ready to accept the
second part of the code. This does not mean that
the first 32 bits match the tuning protection code,
simply that it was correctly stored for the compar-
ing. If b7 = ‘0’, the user must wait for this bit setting
(refer to write cycle AC timings).
The first write cycle issues the Tuning
Protection Unlock Setup command (78h).
The second write cycle inputs the first 32 bits
of the tuning protection code on the data bus,
at address 00000h.
Code, for suggested flowcharts on using
Figure 21., Program Suspend &
Code, and
Figure