ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 55

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
When synchronization is enabled, the controller takes the SYNI signal, adds the t
generate the internal synchronization reference clock, as shown in Figure 40. Each channel then uses the reference clock (or a multiple of
the reference clock if programmed in Register 0xFE0A, Register 0xFE0B, or Register 0xFE0C) to generate its own clock. Register 0xFE0D
is used to set the t
Table 37. Register 0xFE0D—Frequency Synchronization Delay Time
Bits
[7:0]
Table 38. Register 0xFE0E—SYNO Selection and Synchronization Enable
Bits
[7:4]
3
2
1
0
Table 39. Register 0xFE0F—Flag/Synchronization Pin Functions
Bits
7
6
5
4
3
2
1
0
Bit Name
t
Bit Name
Reserved
SYNO selection
Enable Channel C
synchronization
Enable Channel B
synchronization
Enable Channel A
synchronization
Bit Name
Reserved
Channel B filter
180° interleaving
FLAGOUT polarity
FLAGOUT selection
FLGO/SYNO pin
function selection
FLAGIN polarity
FLAGIN debounce
time
FLGI/SYNI pin
function selection
SYNC_DELAY
SYNC_DELAY
time.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CLOCKSYNC
SYNI
Description
This register sets the additional delay of the synchronization reference clock to the rising edge of
the SYNI pin signal. Each LSB corresponds to 80 ns resolution.
Description
Reserved.
0 = select Channel C as the SYNO reference.
1 = select Channel A as the SYNO reference.
Setting this bit enables frequency synchronization for Channel C.
Setting this bit enables frequency synchronization for Channel B.
Setting this bit enables frequency synchronization for Channel A.
Description
Reserved.
Setting this bit enables 180° interleaving on the clock for the ADC and filter of Channel B. This
setting prevents additional delays when the PWM outputs in Channel B use 180° interleaving.
Setting this bit inverts the polarity of the FLGO/SYNO pin signal when the pin is programmed as
a flag output (FLAGOUT).
0 = normal mode. A high signal on the FLGO/SYNO pin sets FLAGOUT.
1 = inverted. A low signal on the FLGO/SYNO pin sets FLAGOUT.
This bit configures the FLGO/SYNO pin to respond to the LIGHTLOAD_A or LIGHTLOAD_B flag.
0 = LIGHTLOAD_A flag triggers FLAGOUT.
1 = LIGHTLOAD_B flag triggers FLAGOUT.
This bit configures the FLGO/SYNO pin as a flag output or a synchronization output.
0 = FLGO/SYNO pin used as a synchronization output (SYNO).
1 = FLGO/SYNO pin used as a flag output (FLAGOUT).
Setting this bit inverts the polarity of the FLGI/SYNI pin signal when the pin is programmed as a
flag input (FLAGIN).
0 = normal mode. A high signal on the FLGI/SYNI pin sets FLAGIN.
1 = inverted. A low signal on the FLGI/SYNI pin sets FLAGIN.
This bit sets the debounce time for FLAGIN.
0 = 0 μs debounce time for FLAGIN.
1 = 100 μs debounce time for FLAGIN.
This bit configures the FLGI/SYNI pin as a flag input or a synchronization input.
0 = FLGI/SYNI pin used as a synchronization input (SYNI).
1 = FLGI/SYNI pin used as a flag input (FLAGIN).
760ns +
t
Figure 40. Synchronization Timing
SYNC_DELAY
Rev. A | Page 55 of 84
t
0
SYNC_DELAY
, together with the 760 ns propagation delay, to
t
S
ADP1053