ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 69

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
LIGHT LOAD PWM DISABLE REGISTERS
Table 99. Register 0xFE69—Channel A Light Load Mode PWM Output Disable
Bits
7
6
5
4
3
2
1
0
Table 100. Register 0xFE6A—Channel B Light Load Mode PWM Output Disable
Bits
7
6
5
4
3
2
1
0
FAST OCP AND CHANNEL C CURRENT SENSE SETTING REGISTERS
Table 101. Register 0xFE6B—CS1_A Blanking Reference Edge
Bits
[7:4]
3
2
1
0
Bit Name
OUT8 disable
OUT7 disable
OUT6 disable
OUT5 disable
OUT4 disable
OUT3 disable
OUT2 disable
OUT1 disable
Bit Name
OUT8 disable
OUT7 disable
OUT6 disable
OUT5 disable
OUT4 disable
OUT3 disable
OUT2 disable
OUT1 disable
Bit Name
Reserved
OUT6 rising edge
blanking
OUT5 rising edge
blanking
OUT2 rising edge
blanking
OUT1 rising edge
blanking
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Description
Description
Reserved.
This bit specifies whether the blanking time for the CS1_A OCP comparator is referenced to the
rising edge of OUT6.
0 = no blanking at OUT6 rising edge.
1 = blanking time referenced to OUT6 rising edge.
This bit specifies whether the blanking time for the CS1_A OCP comparator is referenced to the
rising edge of OUT5.
0 = no blanking at OUT5 rising edge.
1 = blanking time referenced to OUT5 rising edge.
This bit specifies whether the blanking time for the CS1_A OCP comparator is referenced to the
rising edge of OUT2.
0 = no blanking at OUT2 rising edge.
1 = blanking time referenced to OUT2 rising edge.
This bit specifies whether the blanking time for the CS1_A OCP comparator is referenced to the
rising edge of OUT1.
0 = no blanking at OUT1 rising edge.
1 = blanking time referenced to OUT1 rising edge.
Setting this bit disables the OUT8 output when Channel A is in light load mode.
Setting this bit disables the OUT7 output when Channel A is in light load mode.
Setting this bit disables the OUT6 output when Channel A is in light load mode.
Setting this bit disables the OUT5 output when Channel A is in light load mode.
Setting this bit disables the OUT4 output when Channel A is in light load mode.
Setting this bit disables the OUT3 output when Channel A is in light load mode.
Setting this bit disables the OUT2 output when Channel A is in light load mode.
Setting this bit disables the OUT1 output when Channel A is in light load mode.
Setting this bit disables the OUT8 output when Channel B is in light load mode.
Setting this bit disables the OUT7 output when Channel B is in light load mode.
Setting this bit disables the OUT6 output when Channel B is in light load mode.
Setting this bit disables the OUT5 output when Channel B is in light load mode.
Setting this bit disables the OUT4 output when Channel B is in light load mode.
Setting this bit disables the OUT3 output when Channel B is in light load mode.
Setting this bit disables the OUT2 output when Channel B is in light load mode.
Setting this bit disables the OUT1 output when Channel B is in light load mode.
Rev. A | Page 69 of 84
ADP1053