ADP1053 AD [Analog Devices], ADP1053 Datasheet - Page 75

• Manufacturer Part Number: ADP1053
• Description: 3-Channel Digital
• Manufacturer: AD [Analog Devices]

Data Sheet
Table 115. Register 0xFE7A—Channel B PSON Setting
Bits
7
6
[5:4]
[3:2]
[1:0]
Table 116. Register 0xFE7B—Additional Flag Reenable Delay and Channel C PSON Setting
Bits
7
6
5
4
[3:2]
[1:0]
Bit Name
PSON_B polarity
Software PSON_B
PSON_B control
hardware/software
selection
PSON_B delay
PSOFF_B delay
Bit Name
Channel C
additional flag
reenable delay
Channel B
additional flag
reenable delay
Channel A
additional flag
reenable delay
PSON_C control
selection
PSON_C delay
PSOFF_C delay
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Setting this bit inverts the polarity of the PSON_B pin signal when hardware PSON_B is used.
0 = normal mode. A high signal on the PSON_B pin turns on Channel B.
1 = inverted. A low signal on the PSON_B pin turns on Channel B.
When software PSON_B is used, setting this bit turns on Channel B.
These bits specify which signal or signals are used as the PSON_B control.
Bit 5
0
0
1
1
These bits specify the delay from when the PSON_B signal is set to when the soft start of Channel B begins.
Bit 3
0
0
1
1
These bits specify the delay from when the PSON_B signal is cleared to when Channel B is turned off.
Bit 1
0
0
1
1
Description
This bit specifies whether an additional PSON_C delay is added to the reenable delay after a flag is
cleared and before Channel C begins a soft start.
0 = no additional delay is added to the reenable delay.
1 = additional PSON_C delay is added to the reenable delay.
This bit specifies whether an additional PSON_B delay is added to the reenable delay after a flag is
cleared and before Channel B begins a soft start.
0 = no additional delay is added to the reenable delay.
1 = additional PSON_B delay is added to the reenable delay.
This bit specifies whether an additional PSON_A delay is added to the reenable delay after a flag is
cleared and before Channel A begins a soft start.
0 = no additional delay is added to the reenable delay.
1 = additional PSON_A delay is added to the reenable delay.
0 = Channel C is always on.
1 = Either PSON_A or PSON_B must be set to turn on Channel C.
These bits specify the delay from when the PSON_C signal is set to when the soft start of Channel C begins.
Bit 3
0
0
1
1
These bits specify the delay from when the PSON_C signal is cleared to when Channel C is turned off.
Bit 1
0
0
1
1
Bit 4
0
1
0
1
Bit 2
0
1
0
1
Bit 0
0
1
0
1
Bit 2
0
1
0
1
Bit 0
0
1
0
1
PSON_B Control Selection
Always on. Channel B is always on.
Hardware PSON_B. The PSON_B pin turns Channel B on and off.
Software PSON_B. Bit 6 turns Channel B on and off.
Software and hardware PSON_B. Both the PSON_B pin and Bit 6 must be set
to turn on Channel B.
Typical Delay Time
0 ms
50 ms
250 ms
1 sec
Typical Delay Time
0 ms
50 ms
250 ms
1 sec
Typical Delay Time
0 ms
50 ms
250 ms
1 sec
Typical Delay Time
0 ms
50 ms
250 ms
1 sec
Rev. A | Page 75 of 84
ADP1053