L9825_03 STMICROELECTRONICS [STMicroelectronics], L9825_03 Datasheet - Page 6

• Manufacturer Part Number: L9825_03
• Description: Octal Low-side Driver For Resistive and Inductive Loads With Serial / Parallel Input Control, Output Protection and Diagnostic
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

L9825
FUNCTIONAL DESCRIPTION
General
The L9825 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using
the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power
outputs features voltage clamping function for flyback current recirculation and are protected against short cir-
cuit to Vbat.
The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 1 to 6 , overcurrent and ther-
mal overload for outputs 7 and 8 in switch-on condition and 2) open load or short to GND in switch-off condition
for all outputs. The outputs status can be read out via the serial interface.
The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes
signal.
Output Stages Control
Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1
and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These
inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open.
The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1.
The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every
falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers.
Figure 1. Timing of the Serial Interface
The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and
the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since
the last NCS falling edge. The NCS changes only at low CLK.
Table 1. Outputs Control
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Outputs 1, 2:
NON1,2
SPI-bit 1,2
Output 1, 2
NCS
CLK
SDO
SDI
tsclch
tcsdv
thclcl
not defined
off
1
0
tpcld
tscld
tclh
on
0
0
D8
D8
on
thcld
0
1
tcll
on
1
1
D7
Outputs 3 to 8:
SPI-bit 3...8
Output 3...8
D1
tsclcl
D1
tpchdz
off
0
thclch
on
1