IR3895MPBF IRF [International Rectifier], IR3895MPBF Datasheet - Page 31

• Manufacturer Part Number: IR3895MPBF
• Description: 16A HIGHLY INTERGRATED SUPLRBUCK
• Manufacturer: IRF [International Rectifier]

The small signal value may be obtained from the
manufacturer’s datasheets, design tools or SPICE
models. Alternatively, they may also be inferred from
measuring the power stage transfer function of the
converter and measuring the double pole frequency F
and using equation (17)
to compute the small signal C
These result in:
Select crossover frequency F
Since F
pole and zeros.
Detailed calculation of compensation Type III:
Desired Phase Boost Θ = 70°
Select:
Select C
Calculate R
Select R
C
C
2
3
F
F
F


LC
ESR
s
/2=300 kHz
R
2 *
=19.1 kHz
2 *
LC
=1.8 MHz

3

4
3
<F
= 3.3nF.
= 1.78 kΩ:

F
F
0
F
F
3
2 *
1
1
<Fs/2<F
, C
F
P
Z
P
Z

31
2
1
3
Z
1
*
2
3
*


and C
F

R
R
F
F
0.5*
P
3
3
o
F
3
o
C
;
;
o
*

AUGUST 08, 2012 | DATA SHEET| Rev 3.1
ESR
C
4
C
1 sin
1 sin
L
0.5*
2
, Type III is selected to place the
1 sin
1 sin
*
3
2


F
:
o

V


*
Z

in
2
C
12.7 nF, Select:
298 pF, Select:
F

o
s
*
0



=80 kHz
o


V
7.1 kHz and
.
300 kHz
osc


454.0 kHz
14.1 kHz
;
R
3
Single‐Input Voltage, Synchronous Buck Regulator


1.59 kΩ
C
C
2
3


220 pF
10 nF
LC
- 31 -P
16A Highly Integrated SupIRBuck
Calculate R
Select R
Setting the Power Good Threshold
In this design IR3895 is used in normal (non‐tracking,
non‐sequencing) mode, therefore the PGood thresholds
are internally set at 90% and 120% of Vref. At startup as
soon as Vsns voltage reaches 0.9*0.5V=0.45V (Fig. 15),
and after 1.28ms delay, PGood signal is asserted. As long
as the Vsns voltage is between the threshold range,
Enable is high, and no fault happens, the PGood remains
high.
The following formula can be used to set the PGood
threshold. V
Choose R8=2.87KΩ.
The PGood is an open drain output. Hence, it is necessary
to use a pull up resistor, R
value of the pull‐up resistor must be chosen such as to
limit the current flowing into the PGood pin to be less
than 5mA when the output voltage is not in regulation. A
typical value used is 49.9kΩ.
OVP comparator also uses Vsns signal for over Voltage
dectection.With above values for R7 and R8, OVP trip
point (Vout_
Vref Bypass Capacitor
A minimum value of 100pF bypass capacitor is
recommended to be placed between Vref and Gnd pins.
This capacitor should be placed as close as possible to
Vref pin
Vout
R
R
6
4


V V
_
2 *
o

OVP
V
5
= 4.02 kΩ:
-
R
ref
R
R
5
4

C
7 (
7 4.02
ref
, R

out (PGood
1
OVP)
4
Vref


2 *
*
*
5
and R

F
is
R R
V
P
5
out PGood TH
0.9*
2
;
*1.2 * ( 7
C
_
;
1
(
K
4
TH
6
6
*

:
)
R
Vref
can be taken as 90% of Vout.

F
4
Z
_
2.87 kΩ Select:

2
PG
R
106 Ω, Select:
-
, from PGood pin to Vcc. The
)
R


4
;
1) * 8
R
R
8) / 8 1.44
5
R

R
3.4 kΩ,
IR3895

(34)
PD‐97746
R
R
4
6

V

100 Ω
2.87 kΩ
(35)