DSPIC30F2011 MICROCHIP [Microchip Technology], DSPIC30F2011 Datasheet - Page 73

• Manufacturer Part Number: DSPIC30F2011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

9.0
This section describes the 16-bit General Purpose
(GP) Timer1 module and associated Operational
modes. Figure 9-1 depicts the simplified block diagram
of the 16-bit Timer1 module. The following sections
provide detailed descriptions including setup and con-
trol registers, along with associated block diagrams for
the Operational modes of the timers.
The Timer1 module is a 16-bit timer that serves as the
time counter for the real-time clock or operates as a
free-running interval timer/counter. The 16-bit timer has
the following modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
These operational characteristics are supported:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
• Interrupt on 16-bit Period register match or falling
FIGURE 9-1:
© 2005 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046).
modes
edge of external gate signal
TIMER1 MODULE
SOSCO/
T1IF
Event Flag
SOSCI
T1CK
TGATE
16-BIT TIMER1 MODULE BLOCK DIAGRAM
0
1
Equal
Reset
LPOSCEN
dsPIC30F2011/2012/3012/3013
Comparator x 16
TMR1
PR1
Preliminary
Q
Q
Gate
Sync
CK
T
CY
D
These Operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value preloaded into the Period register PR1, then
resets to ‘0’ and continues to count.
When the CPU goes into the Idle mode, the timer stops
incrementing unless the TSIDL (T1CON<13>) bit = 0.
If TSIDL = 1, the timer module logic resumes the incre-
menting sequence on termination of CPU Idle mode.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer will stop incrementing if TSIDL = 1.
TGATE
1 x
0 1
0 0
TON
TSYNC
1
0
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Sync
2
DS70139C-page 71