T89C51RD2-3CSCL ATMEL [ATMEL Corporation], T89C51RD2-3CSCL Datasheet - Page 43
T89C51RD2-3CSCL
Manufacturer Part Number
T89C51RD2-3CSCL
Description
0 to 40 MHz Flash Programmable 8-bit Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.T89C51RD2-3CSCL.pdf
(104 pages)
- Current page: 43 of 104
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Warm Reset
Watchdog Reset
4243G–8051–05/03
Table 26. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor
Note:
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
As detailed in Section “Watchdog Timer”, the WDT generates a 96-clock period pulse
on the RST pin. In order to properly propagate this pulse to the rest of the application in
case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be
added as shown Figure 18.
Figure 18. Reset Circuitry for WDT Reset-out Usage
Start-Up Time
Oscillator
20 ms
These values assume V
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
5 ms
VDD
VDD
VSS
+
RST
1K
820 nF
2.7 µF
1 ms
DD
RST
starts from 0V to the nominal value. If the time between 2
VSS
VDD
P
VDD Rise Time
10 ms
1.2 µF
3.9 µF
T89C51RD2
From WDT
Reset Source
To CPU Core
and Peripherals
To Other
On-board
Circuitry
100 ms
12 µF
12 µF
(1)
43
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