ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 101

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

15.9
15.9.1
2545T–AVR–05/11
Register description
TCCR0A – Timer/counter control register A
• Bits 7:6 – COM0A1:0: Compare match output A mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 15-2.
Table 15-3
mode.
Table 15-3.
Note:
Bit
0x24 (0x44)
Read/write
Initial value
COM0A1
COM0A1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 96
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
Compare output mode, non-PWM mode.
Compare output mode, fast PWM mode
COM0A1
R/W
COM0A0
COM0A0
7
0
for more details.
0
1
0
1
0
1
0
1
Table 15-2
COM0A0
R/W
6
0
Description
Normal port operation, OC0A disconnected
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Description
Normal port operation, OC0A disconnected
WGM02 = 0: Normal port operation, OC0A disconnected
WGM02 = 1: Toggle OC0A on compare match
Clear OC0A on compare match, set OC0A at BOTTOM,
(non-inverting mode)
Set OC0A on compare match, clear OC0A at BOTTOM,
(inverting mode)
shows the COM0A1:0 bit functionality when the WGM02:0 bits
COM0B1
R/W
5
0
COM0B0
R/W
4
0
R
(1)
3
–
0
.
ATmega48/88/168
R
2
–
0
WGM01
R/W
1
0
“Fast PWM mode” on
WGM00
R/W
0
0
TCCR0A
101