ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 135

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

16.11.7
16.11.8
2545T–AVR–05/11
ICR1H and ICR1L – Input capture register 1
TIMSK1 – Timer/Counter1 interrupt mask register
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7, 6 – Res: Reserved bits
These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, input capture interrupt enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4, 3 – Res: Reserved bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, output compare B match interrupt enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, output compare A match interrupt enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, overflow interrupt enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See
Bit
(0x87)
(0x86)
Read/write
Initial value
Bit
(0x6F)
Read/write
Initial value
“Interrupts” on page
(see “Interrupts” on page
See “Accessing 16-bit registers” on page 110.
R/W
(see “Interrupts” on page
(see “Interrupts” on page
R
7
0
7
–
0
R/W
56) is executed when the TOV1 Flag, located in TIFR1, is set.
R
6
0
6
–
0
56) is executed when the ICF1 Flag, located in TIFR1, is set.
ICIE1
R/W
R/W
5
0
5
0
R/W
56) is executed when the OCF1B Flag, located in
56) is executed when the OCF1A Flag, located in
R
4
–
0
4
0
ICR1[15:8]
ICR1[7:0]
R/W
R
3
–
0
3
0
OCIE1B
R/W
R/W
ATmega48/88/168
2
0
2
0
OCIE1A
R/W
R/W
1
0
1
0
TOIE1
R/W
R/W
0
0
0
0
TIMSK1
ICR1H
ICR1L
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