ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 20
ATMEGA48V_11
Manufacturer Part Number
ATMEGA48V_11
Description
8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA48V_11.pdf
(377 pages)
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8.4
8.4.1
8.4.2
2545T–AVR–05/11
EEPROM data memory
EEPROM read/write access
Preventing EEPROM corruption
Figure 8-4.
The Atmel ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and
the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
“Memory programming” on page 285
in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
During periods of low V
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
“Preventing EEPROM corruption” on page 20
Address
clk
On-chip data SRAM access cycles.
Data
Data
WR
CPU
RD
CC
is likely to rise or fall slowly on power-up/down. This causes the device for
CC,
the EEPROM data can be corrupted because the supply voltage is
Compute address
T1
Memory access instruction
contains a detailed description on EEPROM Programming
Address valid
Table 8-2 on page
T2
for details on how to avoid problems in
ATmega48/88/168
Next instruction
T3
24. A self-timing function,
20
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