ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 234

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

22.7.5
Table 22-6.
22.7.6
2545T–AVR–05/11
Status code
(TWSR)
prescaler bits
are 0
0xF8
0x00
Miscellaneous states
Combining Several TWI Modes
Status of the 2-wire serial bus
and
hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Miscellaneous states.
2-wire serial interface
Figure 22-18. Formats and states in the slave transmitter mode.
There are two status codes that do not correspond to a defined TWI state, see
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
To/from TWDR
No TWDR action
No TWDR action
From master to slave
From slave to master
S
Application software response
SLA
STA
0
No TWCR action
STO
R
1
DATA
To TWCR
$A8
$B0
TWIN
A
A
n
T
1
A
TWE
A
X
DATA
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-wire serial bus. The
prescaler bits are zero or masked to zero
Next action taken by TWI hardware
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Wait or proceed current transfer
ATmega48/88/168
$B8
A
DATA
$C0
$C8
A
A
Table
P or S
All 1's
22-6.
P or S
234