ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 37

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

9.12
9.12.1
9.12.2
2545T–AVR–05/11
Register description
OSCCAL – Oscillator calibration register
CLKPR – Clock prescale register
• Bits 7..0 – CAL7..0: Oscillator calibration value
The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove
process variations from the oscillator frequency. A pre-programmed calibration value is automat-
ically written to this register during chip reset, giving the factory calibrated frequency as specified
in
tor frequency. The oscillator can be calibrated to frequencies as specified in
306. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and flash write accesses, and these write times
will be affected accordingly. If the EEPROM or flash are written, do not calibrate to more than
8.8MHz. Otherwise, the EEPROM or flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the
range.
• Bit 7 – CLKPCE: Clock prescaler change enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 3..0 – CLKPS3..0: Clock prescaler select bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 9-14 on page
Bit
(0x66)
Read/write
Initial value
Bit
(0x61)
Read/write
Initial value
Table 29-1 on page
CLKPCE
CAL7
R/W
R/W
7
7
0
38.
306. The application software can write this register to change the oscilla-
CAL6
R/W
6
R
6
–
0
CAL5
R/W
5
R
5
–
0
Device specific calibration value
CAL4
R/W
4
R
4
–
0
CLKPS3
CAL3
R/W
R/W
3
3
CLKPS2
CAL2
See bit description
R/W
R/W
ATmega48/88/168
2
2
CLKPS1
CAL1
R/W
R/W
1
1
Table 29-1 on page
CLKPS0
CAL0
R/W
R/W
0
0
OSCCAL
CLKPR
37