ATXMEGA128B3-AU ATMEL [ATMEL Corporation], ATXMEGA128B3-AU Datasheet - Page 15

• Manufacturer Part Number: ATXMEGA128B3-AU
• Description: 8/16-bit Atmel XMEGA B3 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

7.6
7.7
7.7.1
7.8
7.9
8074B–AVR–02/12
EEPROM
I/O Memory
Data Memory and Bus Arbitration
Memory Timing
General Purpose I/O Registers
Figure 7-2.
XMEGA B3 devices have EEPROM for nonvolatile data storage. It is either addressable in a
separate data space (default) or memory mapped and accessed in normal data space. The
EEPROM supports both byte and page access. Memory mapped EEPROM allows highly effi-
cient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible
using load and store instructions. Memory mapped EEPROM will always start at hexadecimal
address 0x1000.
The status and configuration registers for peripherals and modules, including the CPU, are
addressable through I/O memory locations. All I/O locations can be accessed by the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between
the 32 registers in the register file and the I/O memory. The IN and OUT instructions can
address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 -
0x1F, single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA B3 is shown in the
eral Module Address Map” on page
The lowest 4 I/O memory addresses are reserved as general purpose I/O registers. These regis-
ters can be used for storing global variables and flags, as they are directly bit-accessible using
the SBI, CBI, SBIS, and SBIC instructions.
Since the data memory is organized as four separate sets of memories, the different bus mas-
ters (CPU, DMA controller read and DMA controller write, etc.) can access different memory
sections at the same time.
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes
one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are avail-
able every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for
read. For burst read, new data are available every second cycle. Refer to the instruction sum-
mary for more details on instructions and instruction timing.
Byte Address
17FF
3FFF
1000
2000
FFF
Data Memory Map (Hexadecimal address)
0
ATxmega128B3
Internal SRAM
I/O Registers
RESERVED
EEPROM
(4K)
(2K)
(8K)
61.
Byte Address
2FFF
17FF
1000
2000
FFF
0
ATxmega64B3
Internal SRAM
I/O Registers
RESERVED
EEPROM
(4K)
(2K)
(4K)
XMEGA B3
”Periph-
15