ATXMEGA128B3-AU ATMEL [ATMEL Corporation], ATXMEGA128B3-AU Datasheet - Page 17

• Manufacturer Part Number: ATXMEGA128B3-AU
• Description: 8/16-bit Atmel XMEGA B3 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

8. DMAC – Direct Memory Access Controller
8.1
8.2
8074B–AVR–02/12
Features
Overview
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The two-channel direct memory access (DMA) controller can transfer data between memories
and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates
with minimum CPU intervention, and frees up CPU time. The four DMA channels enable up to
four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations
and directly between peripheral registers. With access to all peripherals, the DMA controller can
handle automatic transfer of data to/from communication modules. The DMA controller can also
read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of
configurable size from 1 byte to 64KB. A repeat counter can be used to repeat each block trans-
fer for single transactions up to 16MB. Source and destination addressing can be static,
incremental or decremental. Automatic reload of source and/or destination addresses can be
done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The two DMA channels have individual configuration and control settings. This include source,
destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Inter-
rupt requests can be generated when a transaction is complete or when the DMA controller
detects an error on a DMA channel.
To allow for continuous transfers, the channels can be interlinked so that the second takes over
the transfer when the first is finished, and vice versa.
Allows high speed data transfers with minimal CPU intervention
Two DMA channels with separate
Programmable channel priority
From 1 byte to 16MB of data in a single transaction
Multiple addressing modes
Optional reload of source and destination addresses at the end of each
Optional interrupt on end of transaction
Optional connection to CRC generator for CRC on DMA data
– from data memory to data memory
– from data memory to peripheral
– from peripheral to data memory
– from peripheral to peripheral
– transfer triggers
– interrupt vectors
– addressing modes
– Up to 64KB block transfers with repeat
– 1, 2, 4, or 8 byte burst transfers
– Static
– Incremental
– Decremental
– Burst
– Block
– Transaction
XMEGA B3
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